September 2-5, 2014
Planet Hollywood Resort
Las Vegas, Nevada, USA

Call for Papers

Newsflash
Final Program available - High-class Panel Discussion confirmed - Google's Paul Eremenko to give Banquet Speech - Only few Hoover Dam Tour Tickets left - Some Sponsorship Opportunities still available......
   |   

Final Program

Program-at-a-Glance (click on picture to download PDF):

At a glance 

SOCC 2014: Program

Day 1: Tuesday, September 2, 2014 - TUTORIAL DAY
7:45am – 4:00pm    Registration
REGISTRATION DESK
9:00am – 5:00pm    Tutorials
Chair: Yuejian Wu, Infinera
   Morning - Tutorial Track A - SUNSET 1
8:30am – 10:00am   

T1A - Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits
M. Tehranipoor
Univ. of Connecticut
10:00am – 10:30am    Coffee Break
FOYER
10:30am – 12:00n    T2A - Clock Implementation: A Question of Timing
G.M. Blair
Avago
   Morning - Tutorial Track B - SUNSET 2
8:30am – 10:00am    T1B - Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges
P. Pande2, A. Nojeh1, A. Ivanov1
1Univ. of British Columbia, Canada, 2Washington State Univ.
10:00am – 10:30am    Coffee Break
FOYER
10:30am – 12:00n    T2B - Carbon Nanotubes and Opportunities for Wireless On-Chip Interconnect
A. Nojeh1, P. Pande2, A. Ivanov1
1Univ. of British Columbia, Canada, 2Washington State Univ.
12:00noon – 01:30pm    Lunch Break
SPICE MARKET BUFFET
   Afternoon - Tutorial Track A - SUNSET 1
1:30pm – 3:00pm    T3A - Design and Management of Multiprocessor System-on-Chips
U.Y. Ogras
Arizona State Univ.
3:00pm – 3:30pm    Coffee Break
FOYER
3:30am – 5:00pm    T4A - System-on-Chip Design Using Tri-Gate Technology
A. Marshall
Univ. of Texas in Dallas
   Afternoon - Tutorial Track B - SUNSET 2
1:30pm – 3:00pm    T3B - Recent Advancements in Fiber Optic Transmission Enabled by Highly Integrated Mixed Signal SoC and Advanced Digital Signal Processing
H. Sun
Infinera
3:00pm – 3:30pm    Coffee Break
FOYER
3:30am – 5:00pm    T4B - Formal Verification in System-on-Chip Design: Scientific Foundations and Practical Methodology
W. Kunz, D. Stoffel, J. Urdahl
Univ. of Kaiserslautem, Germany
    
Day 2: Wednesday, September 3, 2014
7:45am – 4:00pm    Registration
REGISTRATION DESK
8:30am –11:55am    Session WPL - Opening Session, KeyNote and plenary speeches - WILSHIRE A&B
Chair: Kaijian Shi, Cadence Design Systems
Co-Chair: Thomas Buechner, IBM
09:00am – 09:15am    Welcome Note
Kaijian Shi, Cadence Design Systems, General Chair
09:15am – 09:30am    Technical Program Overview
Thomas Buechner, IBM, Technical Program Chair
Danella Zhao, Univ. of Louisiana, Technical Program Co-Chair
09:30am – 10:30am    Keynote: "The Internet of Every-Thing: EDA Perspectives"
Tom Beckley, Senior Vice President of R&D, Cadence Design Systems, Inc.
10:30am – 10:45am    Coffee Break (Sponsored by Cadence Design Systems)
10:45am – 11:45am    “SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH”
Scott Runner, VP of advanced methodologies and low-power design, Qualcomm
11:45am – 01:30pm    Lunch Break
SPICE MARKET BUFFET
1:30pm – 2:45pm    Session WP1A - Low Power Circuits - SUNSET 1
Chair: Gururaj Shamanna, Intel (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Yuejian Wu, Infinera (This email address is being protected from spambots. You need JavaScript enabled to view it.)
1:30pm    Session WP1A - 1    Low-Power High-Speed On-Chip Asynchronous Wave-pipelined CML SerDes
Ashok Jaiswal,  Dominik Walk,  Yuan Fang,  Klaus Hofmann
Technische Universitaet Darmstadt
1:55pm    Session WP1A - 2    A Power Efficient Reconfigurable System-in-Stack: 3D Integration of Accelerators, FPGAs, and DRAM
Peter Gadfort1,  Aravind Dasu1,  Ali Akoglu2,  Yoon Leow2,  Michael Fritze1
1USC Information Sciences Institute, 2University of Arizona
2:20pm    Session WP1A - 3    Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation
Tatsuya Kamakari,  Shinichi Nishizawa,  Tohru Ishihara,  Hidetoshi Onodera
Kyoto University
1:30pm – 2:45pm    Session WP1B - Embedded Systems, Multi/Many Core Systems and Embedded Memory Technologies - SUNSET 2
Chair: Ram Krishnamurthy, Intel (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Oliver Sander, Karlsruhe Institute of Technology (This email address is being protected from spambots. You need JavaScript enabled to view it.)
1:30pm    Session WP1B - 1    Multilayer Layer Graphene Nanoribbon Flash Memory:Analysis of Programming and Erasing Operation
Nahid Hossain1,  Masud Chowdhury1,  Md Belayat Hossain2
1University of Missouri – Kansas City, 2
1:55pm    Session WP1B - 2    CM_ISA++: An Instruction Set for Dynamic Task Scheduling Units for More Than 1000 Cores
Oliver Arnold,  Benedikt Noethen,  Gerhard Fettweis
TU Dresden
2:20pm    Session WP1B - 3    Power aware parallel computing on asymmetric multiprocessor
Sheheeda Manakkadu1,  Sourav Dutta1,  Nazeih Botros2
1Southern Illinois University Carbondale, 2Southern Illinois University
02:45pm – 03:05pm    Coffee Break (Sponsored by Aldec)
FOYER
3:05pm – 4:45pm    Session WP2A - Low Power Methodologies and Architectures - SUNSET 1
Chair: Gururaj Shamanna, Intel (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Sao-Jie Chen, National Taiwan University (This email address is being protected from spambots. You need JavaScript enabled to view it.)
3:05pm    Session WP2A - 1    Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation
Shinichi Nishizawa,  Tohru Ishihara,  Hidetoshi Onodera
Kyoto University
3:30pm    Session WP2A - 2    DESSERT: DESign Space ExploRation Tool based on Power and Energy at System-Level
Santhosh Kumar Rethinagiri1,  Oscar Palomar1,  Adrian Cristal1,  Osman Unsal1,  Michael Swift2
1BSC-Microsoft Research Center, 2University of Wisconsin
3:55pm    Session WP2A - 3    A Novel Ratioed Logic Style for Faster Subthreshold Digital Circuits Based on 90 nm CMOS and Below
Weiwei SHI1 and Chiu-sing CHOY2
1Shenzhen University & Chinese University of Hong Kong, 2Chinese University of Hong Kong
4:20pm    Session WP2A - 4    A CMOS Self-Powered Monolithic Light Direction Sensor with SAR ADC
Hongjiang Song1,  Hongyi Wang2,  Zhijian Lu1,  Tao Luo1,  Jennifer Blain Christen1
1Arizona State University, 2Xi'an Jiaotong University
3:05pm – 4:20pm    Session WP2B - 3D integration - SUNSET 2
Chair: Yuejian Wu, Infinera (This email address is being protected from spambots. You need JavaScript enabled to view it.)
3:05pm    Session WP2B - 1    On Wiring Delays Reduction of Tree-based FPGA using 3-D Fabric
Vinod Pangracious1,  Mohamed Sahbi Marrakchi2,  habib mehrez1,  Zied Marrakchi1
1LIP6, 2Flexras Technologies
3:30pm    Session WP2B - 2    Adaptive Multicast Routing Method for 3D Mesh-based Networks-on-Chip
Poona Bahrebar,  Azarakhsh Jalalvand,  Dirk Stroobandt
Ghent University
3:55pm    Session WP2B - 3    Thermal-Aware Memory Management Unit of 3D-Stacked DRAM for 3D High Definition (HD) Video
Chih-Yuan Chang,  Po-Tsang Huang,  Yi-Chun Chen,  Tian-Sheuan Chang,  Wei Hwang
National Chiao Tung University
4:45pm – 6:15pm    Poster session and reception (food and drinks) - LONDON CLUB
Chair: Thomas Buechner, IBM (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Danella Zhao, Univ. of Louisiana (This email address is being protected from spambots. You need JavaScript enabled to view it.)
   P1    Design of a 9-bit 1GS/s CMOS Folding A/D Converter with a Boundary Error Reduction Technique.
 Jongyoon Hwang1,  Dongjoo Kim1, Munkyo Lee2,  Sunphil Nah3,  Minkyu Song1
1Dongguk.Univ, 2Samsung Thales.CO.Ltd, 3Agency for Defense Development
   P2    Design of a Low Power CMOS 10bit Flash-SAR ADC
Gi-Yoon Lee and Kwang-Sub Yoon
Inha university
   P3    A Systematic Methodology to Design High Power Terahertz and Millimeter-Wave Amplifiers
Siavash Moghadami1,  Farzaneh JalaliBidgoli2,  Shahab Ardalan1
1San Jose State University, 2AmirKabir University of Technology
   P4    A Clock Generator Based on Multiplying Delay-Locked Loop
Chorng-Sii Hwang1,  Ting-Li Chu2,  Wen-Cheng Chen1
1Department of Electrical Engineering National Yunlin University of Science and Technology, 2Graduate School of Engineering Science and Technology National Yunlin University of Science and Technology
   P5    A New Design Methodology for Voltage-to-Time Converters (VTCs) Circuits suitable for Time-Based Analog-to-Digital Converters (T-ADC)
M. Wagih Ismail1 and Hassan Mostafa2
1Electronics and Communications Engineering Department, Cairo University., 2Electronics and Communications Engineering Department, Cairo University
   P6    Reducing the Turn-On Time and Overshoot Voltage for a Diode-Triggered Silicon-Controlled Rectifier during an Electrostatic Discharge Event
Ahmed Ginawi1,  Tian Xia1,  Robert Gauthier2
1University of Vermont, 2IBM
   P7    Electromyograph Data Acquisition and Application using Cypress Programmable System on Chip
Shreeyash Salunke,  Shreyas Darne,  Keval Shah,  Rishikesh Dhamapurkar
Dept of Electrical Engineering,VJTI
   P8    Microcells for ICA-SOC for Remote Sensing of High Energy Radiation
Vijay Jain
University of South Florida
   P9    A Low Supply Voltage Mixed-Signal Maximum Power Point Tracking Controller for Photovoltaic Power System
Jun-Hua Chiang1,  Bin-Da Liu1,  Shih-Ming Chen2,  Hong-Tzer Yang1
1National Cheng Kung University, 2Lite-On Technology Corporation
   P10    Design and Implementation of Novel Source Synchronous interconnection in modern GPU Chips
Tao Li1 and Greg Sadowski2
1AMD dGPU, 2AMD research group
   P11    PVT-Aware Digital Controlled Voltage Regulator Design for Ultra-Low-Power (ULP) DVFS Systems
Pei-Chen Wu1,  Yi-Ping Kuo1,  Chung-Shiang Wu1,  Ching-Te Chuang1,  Yuan-Hua Chu2,  Wei Hwang1
1National Chiao Tung University, Hsin-Chu, Taiwan, 2Industrial Technology Research Institute, Hsin-Chu
   P12    MITH-Dyn : A Multi Vth Dynamic Logic Design Style Using Mixed Mode FinFETs
Ramesh Nair and Ranga Vemuri
University of Cincinnati
   P13    Towards Platform Level Power Management in Mobile Systems
David Kadjo1,  Umit Ogras2,  Raid Ayoub3,  Micheal Kishinevsky3,  Paul Gratz1
1Texas AM University, 2Arizona State University, 3Intel Corporation
   P14    Analysis of the Current-Voltage Characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET)
Azzedin Es-Sakhi and Masud Chowdhury
University of Missouri – Kansas City
   P15    Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET)
Azzedin Es-Sakhi and Masud Chowdhury
University of Missouri – Kansas City
   P16    A Low Power Charge Sharing Hierarchical Bitline and Voltage-Latched Sense Amplifier for SRAM Macro in 28 nm CMOS Technology
Chi-Hao Hong1,  Yi-Wei Chiu1,  Jun-Kai Zhao1,  Shyh-Jye Jou1,  Wen-Tai Wang2,  Reed Lee2
1National Chiao Tung University, 2Global Unichip Corporation
   P17    Networks On Chip Design for Real-Time Systems
Ali Mahdoum
Centre de Développement des Technologies Avancées
   P18    Comparison Between Optimal Interconnection Network in Different 2D and 3D NoC Structures
Farzad Radfar,  Masoud Zabihi,  Reza Sarvari
Sharif University of Technology
   P19    Flow control solution for efficient communication and congestion avoidance in NoC
Ahmed Aldammas,  Adel Soudani,  Abdullah Al-Dhelaan
King Saud University
   P20    Run-Time Voltage Detection Circuit for 3-D IC Power Delivery
Divya Pathak and Ioannis Savidis
Drexel University
   P21    Collision Array Based Workload Assignment for Network-on-Chip Concurrency
He Zhou,  Linda Powers,  Janet Roveda
University of Arizona
   P22    On Circuit Design of On-Chip Non-Blocking Interconnection Networks
Yikun Jiang and Mei Yang
Department of Electrical and Computer Engineering University of Nevada, Las Vegas
   P23    Hardware Architecture of an Internet Protocol Version 6 Processor
Boris Traskov1,  Ulrich Langenbach2,  Klaus Hofmann1,  Peter Gregorius2
1Technische Universitaet Darmstadt, 2Fraunhofer Institut, HHI
   P24    Flexible Reconfigurable Architecture for DSP Applications
Abdulfattah Obeid1,  Syed Manzoor Qasim1,  Mohammed S. BenSaleh1,  Zied Marrakchi2,  Habib Mehrez2,  Heni Ghariani3,  Mohamed Abid3
1KACST, Saudi Arabia, 2LIP6, France, 3CES, ENIS, Tunisia
   P25    Very fast co-simulation model and accurate on-the-fly performance estimation methodology for heterogeneous MPSoC
Nicolas Serna and Francois Verdier
Univ. Nice Sophia Antipolis
8:30pm – 10:00pm    V - The Ultimate Variety Show (Sponsored by Aldec)
V Theater
    
Day 3: Thursday, September 4, 2014
8:00am – 4:00pm    Registration
FOYER
9:00am – 11:10am    Session TPL - Thursday Keynote and Plenary Speech - WILSHIRE A&B
Chair: Kaijian Shi, Cadence Design Systems
9:00am – 10:00am    Keynote: "The Future of Memory/Logic Technologies and Computing System Architectures"
J. Thomas Pawlowski, Fellow and Chief Technologist, Micron Technology, Inc.
10:00am – 10:55am    Plenary: "The Next Generation of Scale-Out Server Architecture : Building the OpenPOWER"
Jeffrey D. Brown, Distinguished Engineer, Emerging Product Development and Hardware Architect, SoC, IBM
10:55am – 11:10am    Coffee Break
FOYER
11:10am – 12:10pm    Session TA1A - Design Track: Power Management and Optimization - SUNSET 1
Chair: Haibo Wang, Southern Illinois University (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Karan Bhatia, Texas Instruments (This email address is being protected from spambots. You need JavaScript enabled to view it.)
11:10am    Session TA1A - 1    Changing power optimization for finFet technology
Gerard M Blair and Bruce E Zahn
LSI Corp
11:30am    Session TA1A - 2    Module-Based Bus Gating Methodology in Low Power SoC Design
Zhe Ge,  Jinglin Zhang,  Miaolin Tan
Freescale Semicondutor
11:50am    Session TA1A - 3    Bus Transaction-Based Frequency and Voltage Regulation
Zhang Lei,  Mei Wangsheng,  Meng Qing,  Brad Hoskins
Freescale Semiconductor
11:10am – 11:50am    Session TA1B - Design Track: Memory and DSP Applications - SUNSET 2
Chair: Mark Schrader, Schrader Consulting (This email address is being protected from spambots. You need JavaScript enabled to view it.)
11:10am    Session TA1B - 1    High Performance Fault Tolerant Memory Management Unit for Space Applications
Xiaofang Chen,  Tianfang Niu,  Sharon Lim
ST Electronics (Satellite Systems)
11:30am    Session TA1B - 2    Development of a system with DSP technology for enhancing electronic nose performance
Cristhian Manuel Durán Acevedo and Isaac Torres López
Faculty of Engineering and Architecture, Research Group in Multisensory Systems and Pattern Recognition, Pamplona University
12:10pm – 01:40pm    Lunch Break
SPICE MARKET BUFFET
1:40pm – 3:20pm    Session TP1A - Data Converters - SUNSET 1
Chair: Poki Chen, National Taiwan University of Science and Technology (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Danella Zhao, Univ. of Louisiana (This email address is being protected from spambots. You need JavaScript enabled to view it.)
1:40pm    Session TP1A - 1    An All-Digital On-Chip Abnormal Temperature Warning Sensor for Dynamic Thermal Management
Ching-Che Chung and Jhih-Wei Li
National Chung Cheng University
2:05pm    Session TP1A - 2    Time Stretcher for a Time-to-Digital Converter with a Precisely Matched Current Mirror
Muhammad Tanveer,  Johan Borg,  Jonny Johansson
Lulea Technical University Sweden
2:30pm    Session TP1A - 3    A 10-Bit 250MS/s Low-Glitch Binary-Weighted Digital-to-Analog Converter
Fang-Ting Chou and Chung-Chih Hung
National Chiao Tung University
2:55pm    Session TP1A - 4    An Accelerated Successive Approximation Technique for Analog to Digital Converter Design
Haibo Wang and Ram Harshvardhan Radhakrishnan
Southern Illinois University
1:40pm – 3:20pm    Session TP1B - Networks on Chip - SUNSET 2
Chair: Danella Zhao, Univ. of Louisiana (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Sakir Sezer, Queen's University Belfast (This email address is being protected from spambots. You need JavaScript enabled to view it.)
1:40pm    Session TP1B - 1    An Energy Efficient Wireless Network-on-Chip using Power-Gated Transceivers
Hemanta Kumar Mondal and Sujay Deb
Indraprastha Institute of Information Technology, Delhi
2:05pm    Session TP1B - 2    Heterogeneous Photonic Network-on-Chip with Dynamic Bandwidth Allocation
Ankit Shah,  Naseef Mansoor,  Ben Johnstone,  Amlan Ganguly,  Sonia Lopez-Alarcon
Rochester Institute of Technology
2:30pm    Session TP1B - 3    Benefits and Costs of Prediction Based DVFS for NoCs at Router Level
Cristinel Ababei1 and Nicholas Mastronarde2
1Marquette University, 2University at Buffalo
2:55pm    Session TP1B - 4    Wiring Resource Minimization for Physically-Complex Network-on-Chip Architectures
Nickvash Kani and Azad Naeemi
Georgia Institute of Technology
1:40pm – 3:20pm    Session TP1C - System Level Design - SUNSET 3
Chair: Sao-Jie Chen, National Taiwan University (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Mark Schrader, Schrader Consulting (This email address is being protected from spambots. You need JavaScript enabled to view it.)
1:40pm    Session TP1C - 1    A Framework for Specifying, Modeling, Implementation and Verification of SOC Protocols
Shahid Ikram,  Isam Akkawi,  Jack Perveiler,  David Asher,  Jim Ellis
Cavium Networks
2:05pm    Session TP1C - 2    Reliability Aware Logic Synthesis through Rewriting
Satish Grandhi1,  Christian Spagnol1,  Jiaoyan Chen1,  Emanuel Popovici1,  Sorin Cotafona2
1University College Cork, 2TU Delft
2:30pm    Session TP1C - 3    Solar-Supercapacitor Harvesting System Design for Energy-Aware Applications
Moeen Hassanalieragh,  Tolga Soyata,  Andrew Nadeau,  Gaurav Sharma
University of Rochester
2:55pm    Session TP1C - 4    Methodology of Exploring ESL/RTL Many-Core Platforms for Developing Embedded Parallel Applications
Jyu-Yuan Lai1,  Chih-Tsun Huang1,  Ting-Shuo Hsu1,  Jing-Jia Liou1,  Tung-Hua Yeh2,  Liang-Chia Cheng2,  Juin-Ming Lu2
1National Tsing Hua University, 2Industrial Technology Research Institute
3:20pm – 3:40pm    Coffee Break
FOYER
3:40pm – 5:20pm    Session TP2A - DSP Architectures and Methodologies - SUNSET 1
Chair: Tobias Noll, RWTH Aachen University (This email address is being protected from spambots. You need JavaScript enabled to view it.)
3:40pm    Session TP2A - 1    Evaluating Mobile SOCs as an Energy Efficient DSP Platform
Matt Briggs and Payman Zarkesh-Ha
University of New Mexico
4:05pm    Session TP2A - 2    New Quantization Error Assessment Methodology for Fixed-Point Pipeline FFT Processor Design
Chen Yang1,  Yizhuang Xie1,  He Chen1,  Yi Deng2
1School of Information and Electronics,Beijing Institute of Technology,Beijing,China, 2Department of Electrical and Computer Engineering,Virginia Polytechnic Institute and State University,Arlington, VA, USA
4:30pm    Session TP2A - 3    Energy Scalable Approximate DCT Architecture Trading Quality via Boundary Error-resiliency
Bharat Garg,  Nitesh K Bharadwaj,  G K Sharma
ABV-Indian Institute of Information Technology and Management Gwalior
4:55pm    Session TP2A - 4    Compensating Imperfections in RF-DAC Based Transmitters Using LUT-Based Predistortion
Bastian Mohr,  Ye Zhang,  Jan Henning Mueller,  Stefan Heinen
RWTH Aachen University
3:40pm – 5:20pm    Session TP2B - Testability and Manufacturability - SUNSET 2
Chair: Chris Ryan, Maxim Integrated (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Martin Margala, University of Massachusetts Lowell (This email address is being protected from spambots. You need JavaScript enabled to view it.)
3:40pm    Session TP2B - 1    Errors in Solving Inverse Problem for Reversing RTN Effects on VCCmin Shift in SRAM Reliablity Screening Test Designs
Hiroyuki Yamauchi and Worawit Somha
Fukuoka Institute of Technology
4:05pm    Session TP2B - 2    Cost-Optimal Design of Wireless Pre-bonding Test Framework
Unni Chandran,  Danella Zhao
University of Louisiana at Lafayette
4:30pm    Session TP2B - 3    IP Watermark Verification Based on Power Consumption Analysis
Cédric Marchand1,  Lilian Bossuet1,  Edward Jung2
1Laboratoire Hubert Curien, UMR CNRS 5516, University of Lyon, Saint-Etienne, France, 2School of Computing and Software Engineering, Southern Polytechnic State University, GA, USA
4:55pm    Session TP2B - 4    A Unique Non-intrusive Approach to Non-ATE Based cul-de-sac SoC Debug
Vasant Easwaran,  Virendra Bansal,  Greg Shurtz,  Rahul Gulati,  Mihir Mody,  Prashant Karandikar,  Prithvi Shankar Y.A.
Texas Instruments Inc.
3:40pm – 5:20pm    Session TP2C - Reconfigurable and Programmable Circuits and Systems - SUNSET 3
Chair: Oliver Sander, Karlsruhe Institute of Technology (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Helen Li, University of Pittsburgh (This email address is being protected from spambots. You need JavaScript enabled to view it.)
3:40pm    Session TP2C - 1    REFLEX: Reconfigurable Logic for Entropy Extraction
Vikram Suresh and Wayne Burleson
University of Massachusetts, Amherst
4:05pm    Session TP2C - 2    A Reconfigurable 0-L1-L2 S-MASH2 Modulator with High-Level Sizing and Power Estimation
Abhilash K N and Srinivas .M.B
BITS Pilani, Hyderabad Campus
4:30pm    Session TP2C - 3    A Configurable Packet Classification Architecture for Software-Defined Networking
Keissy Guerra Perez,  Xin Yang,  Sandra Scott-Hayward,  Sakir Sezer
Queen's University Belfast
4:55pm    Session TP2C - 4    A Stochastic Learning Algorithm for Neuromemristive Systems
Cory Merkel and Dhireesha Kudithipudi
Rochester Institute of Technology
5:20pm – 5:30pm    Coffee Break
FOYER
5:30pm – 7:00pm    Panel Discussion - WILSHIRE A&B
Chair: Thomas Buechner, IBM
                                The End of the Microprocessor Chip - Will SoCs dominate computing?
Panelists:
Jeffrey D. Brown, Distinguished Engineer, Emerging Product Development and Hardware Architect, SoC, IBM
Norris Ip, Solutions Group Director, Cadence
Ram Krishnamurthy, Head of High Performance and Low Voltage Circuits Group, Intel Labs
Nigel Paver, ARM Fellow
Sakir Sezer, Director of Research, ECIT, Queen's University Belfast and CTO, titanic systems
7:00pm – 9:00pm    Banquet Dinner - LONDON CLUB
Chair: Kaijian Shi, Cadence Design Systems
                                Banquet Speech: "Democratizing the mobile hardware ecosystem: Google's Project Ara"
Paul Eremenko, Director, Project Ara, Google
    
Day 4: Friday, September 5, 2014
8:30am – 11:00am    Registration
FOYER
9:00am – 10:15am    Session FA1A - Special Session: Memristor-based Processors - SUNSET 1
Chair: Dhireesha Kudithipudi, Rochester Institute of Technology (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Garrett Rose, AirForce Research Laboratories
9:00am    Session FA1A - 1    On Designing Primitives for Cortical Processors with Memristive Hardware
Dhireesha Kudithipudi1,  Cory Merkel1,  Yu Kee Ooi1,  Qutaiba Saleh1,  Garrett S. Rose2
1NanoComputing Research Lab, Rochester Institute of Technology, 2AFRL - Information Directorate
9:25am    Session FA1A - 2    Emerging Memristor Technology Enabled Next Generation Cortical Processor
Hai Li1,  Miao Hu1,  Xiaoxiao Liu1,  Mengjie Mao1,  Chuandong Li2,  Shukai Duan2
1University of Pittsburgh, 2Southwest University, China
9:50am    Session FA1A - 3    Energy Efficient Memristor Crossbar Based Multicore Neuromorphic Processors
Tarek Taha,  Raqibul Hasan,  Chris Yakopcic
University of Dayton
9:00am – 09:50am    Session FA1B - Analog Circuits - SUNSET 2
Chair: Poki Chen, National Taiwan University of Science and Technology (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Hongjiang Song, Intel (This email address is being protected from spambots. You need JavaScript enabled to view it.)
9:00am    Session FA1B - 1    Resistorless On-Die High Voltage Power Supply Noise Measurement
Siddharth Katare,  Raj Dua,  Narayanan Natarajan
Intel
9:25am    Session FA1B - 2    Design of a Low Power Multistandard Transceiver Chain Based on Current-reuse VCO
Ye Zhang,  Jan Henning Mueller,  Muh-Dey Wei,  Ralf Wunderlich,  Stefan Heinen
RWTH Aachen
9:50am – 10:40am    Session FA2B - Verification - SUNSET 2
Chair: Poki Chen, National Taiwan University of Science and Technology (This email address is being protected from spambots. You need JavaScript enabled to view it.)
9:50am    Session FA2B - 1    SoC Scan-Chain Verification Utilizing FPGA-based Emulation Platform and SCE-MI Interface
Bill Jason Pidlaoan Tomas1,  Yingtao Jiang2,  Mei Yang2
1Cadence Inc., 2University of Nevada Las Vegas
10:15am    Session FA2B - 2    A New Approach Using Symbolic Analysis to Compute Path-Dependent Effective Properties Preserving Hierarchy
Sridhar Srinivasan,  Ellis Cohen,  Mark Hofmann
Mentor Graphics Corp.
10:40am – 10:55am    Coffee Break
FOYER
10:55am – 12:10pm    Session FA3A - Biomedical Circuits and Systems - SUNSET 1
Chair: Ken Hsu, Rochester Institute of Technology (This email address is being protected from spambots. You need JavaScript enabled to view it.)
10:55am    Session FA3A - 1    A Highly Sensitive ISFET Using pH-to-Current Conversion for Real-Time DNA Sequencing
Mohammad Uzzal1,  Payman Zarkesh-Ha1,  Jeremy Edwards2,  Ezequiel Coelho2,  Priyanka Rawat2
1Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM, USA, 2Molecular Genetics and Microbiology, University of New Mexico, Albuquerque, NM, USA
11:20am    Session FA3A - 2    A Neural Rehabilitation Chip with Neural Recording, Spike Detection, Spike Rate Counter, and Biphasic Neural Stimulator
Hongjiang Song,  Chen Chen,  Meng-Wei Lin,  Kaijun Li,  Jennifer Blain Christen
Arizona State University
11:45am    Session FA3A - 3    High-Frequency and Power-Efficiency Ultrasound Beam-Forming Processor for Handheld Applications
Guo-Zua Wu1,  Song-Nien Tang1,  Chih-Chi Chang1,  Chien-Ju Lee1,  Kuan-Hsien Lin2,  Oscal T.-C. Chen2
1Industrial Technology Research Institute, 2National Chung Cheng University
10:55am – 12:10pm    Session FA3B - Wireless and wireline communication circuits and methodologies - SUNSET 2
Chair: Mark Schrader, Schrader Consulting (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Hongjiang Song, Intel (This email address is being protected from spambots. You need JavaScript enabled to view it.)
10:55am    Session FA3B - 1    A Low Complexity Multi Standard Dual Band CMOS Polar Transmitter for Smart Utility Networks
Jan Henning Mueller,  Ye Zhang,  Lei Liao,  Aytac Atac,  Zhimiao Chen,  Bastian Mohr,  Stefan Heinen
RWTH Aachen University
11:20am    Session FA3B - 2    A 25.5mW 10Gb/s inductorless receiver with an adaptive front-end in 0.13 m CMOS.
Sushrant Monga and Shouri Chatterjee
Indian Institute of Technology, Delhi
11:45am    Session FA3B - 3    A Hardware Acceleration Scheme for Memory-Efficient Flow Processing
Xin Yang,  Sakir Sezer,  Shane O'Neill
Queen's University Belfast
10:55am – 12:10pm    Session FA3C - Advances in SRAM Design - SUNSET 3
Chair: Norbert Schuhmann, Fraunhofer IIS (This email address is being protected from spambots. You need JavaScript enabled to view it.)
Co-Chair: Sakir Sezer, Queen's University Belfast (This email address is being protected from spambots. You need JavaScript enabled to view it.)
10:55am    Session FA3C - 1    A Body-Bias based Current Sense Amplifier for High- Speed Low-Power Embedded SRAMs
Tahseen Shakir and Manoj Sachdev
University of Waterloo
11:20am    Session FA3C - 2    Comparative Study of FinFETs versus 22nm Bulk CMOSs: SRAM Design Perspective
Hooman Farkhani1,  Ali Peiravi2,  Farshad Moradi3
1Aarhus University, 2Ferdowsi University of Mashhad, 3Aarhus Unviersity
11:45am    Session FA3C - 3    A 40nm 256kb 6T SRAM with Threshold Power-Gating, Low-Swing Global Read Bit-Line, and Charge-Sharing Write with Vtrip-Tracking and Negative Source-Line Write-Assists
Chao-Kuei Chung1,  Chien-Yu Lu1,  Zhi-Hao Chang1,  Shyh-Jye Jou1,  Ching-Te Chuang1,  Ming-Hsien Tu2,  Yu-Hsuan Chen2,  Yong-Jyun Hu2,  Paul-Sen Kan2,  Huan-Shun Huang2,  Kuen-Di Lee2,  Yung-Shin Kao2
1National Chiao-Tung University, 2Faraday Technology Corporation
01:00pm – 6:00pm    Hoover Dam Tour
Chair: Venki Muthukumar, University of Nevada Las Vegas

Las Vegas Show

V - The Ultimate Variety Show

V - The Ultimate Variety Show

SOCC 2014 is happy to present their attendees a genuine Las Vegas Show. The show will take place on Wednesday, Sept. 3, 2014, 8:30 PM.

Admission is included in the full (non-student) conference fee and includes VIP seating and a free drink. Additional tickets can be bought via the conference registration and payment page at an SOCC2014 special rate of $55 including VIP seating and a free drink .

V - The Ultimate Variety Show is the ultimate way to experience the best of Las Vegas entertainment all wrapped up in one action packed show. Experience over 14 of the best acts ever to perform on a Vegas stage such as; The Crazy Gaucho's, Melinda: The First Lady of Magic, Prop Comedian Russ Merlin, the Skating Aratas, and much more. Helmed by Las Vegas Show veteran and the world's fastest juggler Wally Eastwood, get ready for an unforgettable ride as each show is different from the last. With our rotating cast of over 14 unique acts, each night offers a new experience guaranteed to please audience members of all ages.

V - The Ultimate Variety Show is playing nightly at the V Theater inside Planet Hollywood Resort & Casino's Miracle Mile Shops.

Video Link: http://youtu.be/k3HRvRAX4eI
Photos @: http://www.vtheshow.com/LasVegasShow/V-The-Show-Photo-Gallery
More Videos @: http://www.vtheshow.com/LasVegasShow/Las-Vegas-Show-Videos

 

Panel Discussion

The End of the Microprocessor Chip - Will SoCs dominate computing?

Moderator: Thomas Buechner, IBM

Panelists:

Jeffrey D. Brown, Distinguished Engineer Emerging Product Development, and Hardware Architect SoC, IBM
Norris Ip, Solutions Group Director, Cadence
Ram Krishnamurthy, Head of High Performance and Low Voltage Circuits Group, Intel Labs
Nigel Paver, ARM Fellow
Sakir Sezer, Director of Research, ECIT, Queen's University Belfast and CTO, titanic systems

Abstract:

Since their rise in the 90's, SoCs have been fueling the rapid growth of mobile devices, consumer electronics, medical equipment, and network infrastructure devices.

Recently, another application of SoC techniques has emerged that may change the computer ecosystem as we know it. The traditional microprocessor chip that used to be the brain of all computing platforms from PCs to high-end servers is more and more being replaced by high complex SoCs integrating numerous processing cores together with memory, bridges, networks-on-chip, hardware accelerators, standard high-speed interfaces, licenced IP blocks, voltage regulators, etc., on a single chip.

With this trend, the traditional processor design methodologies developed over decades now more and more need to be extended or even replaced by SoC design methodologies with their platform-based approach, HW/SW codesign, licensed IP usage, etc. This causes new challenges for both the traditional processor designers and SoC designers, who all need to deal with a new ecosystem and a broader range of skills. Growing complexity, new system aspects, changing tools, etc., require paradigm changes in the way we design, verify, manufacture, and test computer systems. Recent announcements like the creation of the Open Power Foundation by IBM, Nvidia, Google, and others, and like the growing number of server SoCs based on ARM and Intel processor architectures have shown that the industry is actively driving this change.

The panel will address questions like:

  • What are the challenges of this new ecosystem to the developers?
  • Is the industry and academia ready for this trend?
  • Will this be the end of the IDMs? Will we only have pure-play foundries in 5 years from now?
  • Will the "traditional" processor designers become obsolete?
  • What are the skills SoC developers and processor developers need to support this new trend?
  • Is the EDA industry ready to support the growing complexity of those SoCs?
  • What is the impact of new players like Google, Microsoft, Facebook, Apple, etc. in this game, starting to design their own systems or processor SoCs?

Panelists

Jeffrey D. Brown
Distinguished Engineer, Emerging Product Development and Hardware Architect, SoC
IBM

JDB

Jeffrey D. Brown, IBM Server and Technology Group, is an IBM Distinguished Engineer and member of the IBM Academy of Technology.  He received a B.Sc. in Electrical Engineering and a B.Sc. in Physics from Washington State University in 1981.  He received his M.Sc. degree in Electrical Engineering from Washington State University in 1982.  Mr. Brown has over 25 years of experience in VLSI development including processor, memory, and IO subsystem development projects for IBM multi-processor systems and servers.  He is the coauthor of more than 40 patent filings.  He has been the Chief Engineer on several processor and SOC chip development programs including Waternoose for the the Xbox 360® and IBM Power Edge of NetworkTM.  Mr. Brown is presently the chair of the OpenPOWERTM Foundation Technical Steering Committee.

Norris Ip
Solutions Group Director
Cadence

NorrisIpNorris Ip is a Solutions Group Director of the Formal and Automated Verification business unit in the Systems & Verification Group at Cadence Design System.  Norris joined Cadence in 2014 via the acquisition of Jasper, where he was a Fellow at Jasper Design Automation, focused on development of the formal verification platform for RTL development, architectural modeling, IP Register Verification, SoC Connectivity Verification, etc. Prior to joining Jasper, he was a Research Scientist at Cadence Berkeley Labs, developing formal and smart test bench techniques. He also served in the SystemC Verification Working Group.

 

He received a B.A (Honors) in Engineering and Computer Science from Oxford University in 1991, and a Ph.D. in Computer Science from Stanford University in 1997. Norris has over over 20 years of experience in advancing verification techniques for different application domains and is the coauthor of 19 US patents and patent filings.

 

Ram Krishnamurthy
Head of High Performance and Low Voltage Circuits Group
Intel Labs

Ram Krishnamurthy

Ram Krishnamurthy received the B.E. degree in electrical engineering from Regional Engineering College, Trichy, India, in 1993 and Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 1998. He has been with Intel Corporation since 1998, where he is Senior Principal Engineer and heads the high performance and low voltage circuits group at Circuits Research Labs, Intel Labs, Hillsboro, Oregon. He is responsible for research in high performance, energy efficient and low voltage circuits for microprocessors and SoCs, and has worked on circuits research for high performance and low power microprocessors on eight generations of Intel technologies.

He holds 95 issued patents with over 50 patents pending and has published 135 conference/journal papers and 3 book chapters on high-performance energy-efficient microprocessor design. He serves as Intel’s representative on the SRC Integrated Circuits and Systems Sciences Task Force, has been a guest editor of the IEEE Journal of Solid-State Circuits and on the technical program committees of the ISSCC, CICC, and SOCC conferences. He served as the Technical Program Chair/General Chair for the 2005/2006 IEEE International Systems-on-Chip Conference and presently serves on the conference’s steering committee. He serves as ECE department adjunct faculty at Oregon State University, where he taught advanced VLSI design. He also serves on industrial advisory board of Oregon State University and State University of New York at Buffalo ECE departments, and editorial boards of IEEE transactions on VLSI systems and IEEE journal of emerging circuits and systems.

Krishnamurthy has received the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award in 2012, IEEE European Solid State Circuits Conference Best Paper Award in 2012, Outstanding Industry Mentor Award from SRC in 2002 and 2011, Intel Awards for most patents filed in 2001 and most patents issued in 2003, Alumni recognition award from Carnegie Mellon University in 2009, and MIT Technology Review’s TR35 Innovator Award in 2006. He has received the Intel Achievement Award, Intel Corporation’s highest technical award, twice - in 2004 and 2008 for development and technology transfer of novel high-performance execution core arithmetic circuits and special-purpose hardware encryption accelerators. He is a Fellow of the IEEE.

Nigel Paver
ARM Fellow

Nigel PaverNigel Paver is an ARM Fellow with over 24 years of experience in and around the ARM architecture.  He is the Director of Systems Research in the corporate R&D group leading a team investigating end-to-end systems power and performance across a range of emerging ARM market segments.

Nigel received his PhD in Computer Science from the University of Manchester in 1994 where we worked on the AMULET asynchronous implementations of the ARM architecture.  He also holds an MS degree in Systems Design also from Manchester University and a BS degree in Electronics from UMIST.  Nigel holds 31 US patents and has published in excess of 30 papers including best paper awards at; VLSI ’93, ASYNC ’97  & ASYNC ’98, ISPASS’14 and he received the British Computer Society (BCS) Award for his work on AMULET1.

Sakir Sezer
Director of Research, ECIT, Queen's University Belfast and CTO, titanic systems

sakir small 

 

Hoover Dam Tour

Hoover Dam at Night 
Picture by Gayinspandex (Own work) [CC-BY-SA-3.0], ;via Wikimedia Commons

On Friday Sept. 5, 1:00 PM, we will offer a guided bus tour to Hoover Dam, where you can take breathtaking inside and outside views of this engineering masterpiece including its huge generators, Lake Mead, and the Mike O'Callaghan-Pat Tillman Memorial Bridge spanning across the Black Canyon, connecting Nevada and Arizona nearly 900 feet above the Colorado River.

Ticket Price: $49, bookable via the conference payment page. Note that space is limited and we sell tickets on a first-come, first-serve base.

Duration: Approximately 4.5 hours from pick up to drop off

Tour Coach: Passengers will travel on a 56 passenger custom built luxury tour coach. The coach is equipped with a restroom, reclining seats, foot rests, TV monitors throughout.

The tour includes:

  • Complimentary Hotel Pickup (from Planet Hollywood)
  • Complimentary water
  • Hoover Dam Booklet
  • Transportation via fully-equipped deluxe motor coaches Driver/Tour guide
  • Narration of Las Vegas, Henderson and Boulder City
  • Photo opportunities of Lake Mead and Colorado River
  • 2 hours free time at Hoover Dam
    • Visitor Center
    • Exhibit hall
    • Observation Deck
    • Theater
    • Generator Room

Subcategories

Tutorials

Sponsors

MBblue transparent CASnew big trans

Corporate Sponsors

cadence logo Infinera NewLOGOtagline PMS White
Aldec Crescent rgb sm  

Distinguished Speakers

beckley

TOM BECKLEY

Senior Vice President of R&D
Cadence Design Systems, Inc.
runner

SCOTT RUNNER

VP of Advanced Methodologies and Low-Power Design
Qualcomm
pawlowski

J. THOMAS PAWLOWSKI

Fellow and Chief Technologist
Micron Technology, Inc.
 JDB

Jeffrey D. Brown

Distinguished Engineer, Emerging Product Development
IBM
PaulPhotoV

PAUL EREMENKO

Director, Project Ara
Google

 

Latest News

Copyright © 2013 IEEE SOC Conference. Template designed by Hot Joomla Templates

twitter Follow @ieee_socc on Twitter 

top