Senior Vice President of R&D
Cadence Design Systems, Inc.
“The Internet of Every-Thing: EDA Perspectives”
Tom Beckley is senior vice president of the Custom IC & PCB Group. His product responsibilities include the Virtuoso ® design environment, physical design and routing, and simulation product lines for full-custom digital and analog design, infrastructure such as the Open Access database and the process design kits (PDKs) that are essential for physical IC design, and for the Allegro® and OrCAD® design and routing, and Sigrity™ high-speed analysis solutions for printed circuit boards and IC packaging. In addition, Beckley is executive sponsor of the Cadence Quality Initiative, a sustained corporate focus on developing and deploying processes enabling design, implementation and delivery of high-quality, full-featured products.
Beckley joined Cadence in 2004 via the acquisition of Neolinear, where he served as President and CEO. Neolinear developed innovative auto-interactive and automated analog/RF tools and solutions for mixed-signal design. Prior to Neolinear, Beckley was head of the Systems Division at Avant! Corporation. He came to Avant! through the acquisition of Xynetix Design Systems, the market leader in advanced IC packaging and systems-level virtual prototyping, where he was President and CEO. Prior to Xynetix, Beckley held engineering and management positions at Harris Corporation and General Motors.
Beckley received his BS in mathematics and physics from Kalamazoo College and an MBA from Vanderbilt University.
A decade ago it was easy to tell who the semiconductor industry players were, and where they fit relative to customer requirements and the electronics ecosystem. Integrated Circuits, system and software each had their own distinct suppliers and there was a built-in assumption that customers would be able to “make it work”. Today, innovative connected products increasingly require a different paradigm where traditional industry definitions are blurred by the realization that the “Internet of Every-thing” requires a more unified knowledge of products and design solutions in areas from devices to servers, software and infrastructure. This talk will address the challenges and provide visions from EDA perspectives as a key enabler of tomorrow’s technology on these changing industry dynamics - one in which is the need of integrated EDA solutions to meet requirements for increased miniaturization, mixed-signal design, sensors, software and electro-mechanical designs, to enable emerging vertical integrated systems companies and others to prosper.
VP of advanced methodologies and low-power design
“SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH”
Scott Runner is currently the Vice President of Advanced Methodologies and Low Power Design at Qualcomm Technologies, Inc. He has worked in engineering in the semiconductor and EDA industries for 30 years, holding positions as Director of processors and IP, Design Automation and design manager at Conexant Systems Inc., a "founding" member of the DesignWare team at Synopsys Inc., and DSP and ASIC design engineer and Design Center manager at Fujitsu Microelectronics. He has taped out over 48 devices and has authored over 22 papers & articles. He holds a B.S. in Physics with emphasis in Computer Science and EE from Georgia Tech.
Mobile Applications are not only becoming more complex, but they are facing stiff constraints in power and quality & reliability. In the next decade, consumers are going to be treated to an array of new use case experiences in mobility that one can only dream of today. And new areas are emerging with exciting new user experiences in the car, with features known to many smartphone users making their way into the automobile, along with a myriad of other functions that drivers today cannot imagine. The HW and SW IP and systems integration that will enable these experiences are prodigious. Design and verification challenges which must be surmounted to enable such high levels of integration and functionality are daunting. And doing so in the timeframes required to satisfy the appetites of smartphone, tablet and automotive customers, while delivering to cost, power, performance and quality targets demands novel approaches. We will explore these challenges in the design of the most popular devices in the wireless world.
J. Thomas Pawlowski
Fellow and Chief Technologist
Micron Technology, Inc.
“The Future of Memory/Logic Technologies and Computing System Architectures”
J. Thomas Pawlowski is a Fellow and Chief Technologist with Micron’s Architecture Development Group. His responsibilities include evaluating new technologies and investments, exploring new memory and system architectures, and providing guidance to many technical teams, both internally and external to Micron.
Mr. Pawlowski’s experience includes the creation or co-creation of numerous groundbreaking memory architectures and concepts including: synchronous burst pipelined SRAM; hierarchical cache systems; Zero Bus Turnaround SRAM; the first double data rate memory (starting with SRAM and extending to DRAM and NAND technologies); PSRAM; high-speed NAND; the first double address rate memory; the first quad data rate memory; the first multi-channel memory; memories on SERDES buses; RLDRAM (the first DRAM to exceed SRAM performance); refresh and error correction schemes for memory subsystems; the architectural roots of Micron’s HMC device; the first dedicated hardware architecture of Micron’s newly announced nondeterministic Automata Processor; and other projects still in development.
Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada. He also holds approximately 150 U.S. and international patents and serves on several advisory boards, including the Exascale Grand Challenge EAB.
In his spare time, Mr. Pawlowski designs and builds loudspeakers and custom tools, and he has completed 60% of the design of a revolutionary electric car concept.
There is no shortage of scaling challenges facing the computing world: logic and memory scaling, dark silicon, thermal issues, bandwidth, throughput, energy proportionality, and many others. This talk will address these challenges, showing from whence we came and whither we are going. It will paint a picture of the increasing importance and influence of memory technologies and architectures on system performance metrics, discuss the underlying causes, and show the inevitable progression of the relationship between logic and memory. The talk will then turn to Micron’s Automata Processing technology.
The Automata Processor is a fundamentally new computing architecture that leverages the intrinsic parallelism of DRAM. This innovative, nondeterministic, finite Automata Processor tackles NP-hard problems that, until now, have been considered unsolvable—opening up new frontiers of computing. The revelation of the Automata Processor portends a future rich in devices that have memory technology at their core.
Jeffrey D. Brown
Distinguished Engineer, Emerging Product Development and Hardware Architect, SoC
"The Next Generation of Scale-Out Server Architecture : Building the OpenPOWERTM Eco-System"
Jeffrey D. Brown, IBM Server and Technology Group, is an IBM Distinguished Engineer and member of the IBM Academy of Technology. He received a B.Sc. in Electrical Engineering and a B.Sc. in Physics from Washington State University in 1981. He received his M.Sc. degree in Electrical Engineering from Washington State University in 1982. Mr. Brown has over 25 years of experience in VLSI development including processor, memory, and IO subsystem development projects for IBM multi-processor systems and servers. He is the coauthor of more than 40 patent filings. He has been the Chief Engineer on several processor and SOC chip development programs including Waternoose for the the Xbox 360® and IBM Power Edge of NetworkTM. Mr. Brown is presently the chair of the OpenPOWERTM Foundation Technical Steering Committee.
The elephant in the data center is that the price/performance improvement driven by CMOS technology scaling has slowed. Manufacturing costs, power density, and thermal considerations are limiting the ability of developers to exploit the density and performance value of the next technology generation. IBM has partnered with more than 45 companies in the OpenPOWERTM Foundation to open up IBM POWER® systems and processors as a platform for innovation to overcome this problem. The OpenPOWERTM Foundation members are using the POWER8TM design, accelerators, and heterogenous computing to bring forth the next wave of performance scaling. This presentation will explore the motivation, strategy, and key technologies that are being brought to market by foundation members to meet this challenge.
Director, Project Ara
“Democratizing the mobile hardware ecosystem: Google's Project Ara”
Paul Eremenko is currently director of Project Ara at Google, in the Advanced Technology & Projects (ATAP) organization. Previously he was an associate vice president at Motorola, where he led the development of Ara, a project to create a modular hardware ecosystem - rivaling the mobile app ecosystem in pace and level of innovation - around smartphones in an effort to deliver the mobile internet to the next 5 billion people. Paul is also a research affiliate at MIT in the Engineering Systems Division.
Prior to joining Motorola and then Google, Paul directed the Tactical Technology Office (TTO) at the Defense Advanced Research Projects Agency (DARPA), the Pentagon’s principal engine for disruptive innovation. TTO is DARPA’s systems office responsible for all X--‐plane, spacecraft, ground vehicle, and robotics programs, totalling approximately $500 million annually. Previously, Paul developed and led DARPA's advanced design and manufacturing program portfolio, and also served as program manager for several space efforts, including the 100 Year Starship.
Earlier in his career, Paul was an aerospace design engineer, the chief engineer for an unmanned aircraft program, and a management consultant focusing on technology, innovation, and M&A strategies. He has undergraduate and Master's degrees in aeronautics from MIT and Caltech, respectively, and a law degree from Georgetown University. Paul is also a licensed pilot.
Project Ara is an effort in Google’s Advanced Technology & Projects (ATAP) organization to create a modular smartphone platform, with the twin aims of delivering a deep customization experience to users and enabling significantly lowered barrier to entry into the mobile hardware ecosystem. The talk will describe the philosophical underpinnings of Project Ara, its status and timeline, and the opportunities it creates in the mobile processor space as an example. We will also talk about the origins of ATAP and its unique innovation model, inspired by that of the Defense Advanced Research Projects Agency (DARPA).Project Ara is an effort in Google's Advanced Technology & Projects (ATAP) organization to create a modular smartphone platform, with the twin aims of delivering a deep customization experience to users and enabling significantly lowered barrier to entry into the mobile hardware ecosystem. The talk will describe the philosophical underpinnings of Project Ara, its status and timeline, and the opportunities it creates in the mobile processor space as an example. We will also talk about the origins of ATAP and its unique innovation model, inspired by that of the Defense Advanced Research Projects Agency (DARPA).