The End of the Microprocessor Chip - Will SoCs dominate computing?
Moderator: Thomas Buechner, IBM
Panelists:
Jeffrey D. Brown, Distinguished Engineer Emerging Product Development, and Hardware Architect SoC, IBM
Norris Ip, Solutions Group Director, Cadence
Ram Krishnamurthy, Head of High Performance and Low Voltage Circuits Group, Intel Labs
Nigel Paver, ARM Fellow
Sakir Sezer, Director of Research, ECIT, Queen's University Belfast and CTO, titanic systems
Abstract:
Since their rise in the 90's, SoCs have been fueling the rapid growth of mobile devices, consumer electronics, medical equipment, and network infrastructure devices.
Recently, another application of SoC techniques has emerged that may change the computer ecosystem as we know it. The traditional microprocessor chip that used to be the brain of all computing platforms from PCs to high-end servers is more and more being replaced by high complex SoCs integrating numerous processing cores together with memory, bridges, networks-on-chip, hardware accelerators, standard high-speed interfaces, licenced IP blocks, voltage regulators, etc., on a single chip.
With this trend, the traditional processor design methodologies developed over decades now more and more need to be extended or even replaced by SoC design methodologies with their platform-based approach, HW/SW codesign, licensed IP usage, etc. This causes new challenges for both the traditional processor designers and SoC designers, who all need to deal with a new ecosystem and a broader range of skills. Growing complexity, new system aspects, changing tools, etc., require paradigm changes in the way we design, verify, manufacture, and test computer systems. Recent announcements like the creation of the Open Power Foundation by IBM, Nvidia, Google, and others, and like the growing number of server SoCs based on ARM and Intel processor architectures have shown that the industry is actively driving this change.
The panel will address questions like:
- What are the challenges of this new ecosystem to the developers?
- Is the industry and academia ready for this trend?
- Will this be the end of the IDMs? Will we only have pure-play foundries in 5 years from now?
- Will the "traditional" processor designers become obsolete?
- What are the skills SoC developers and processor developers need to support this new trend?
- Is the EDA industry ready to support the growing complexity of those SoCs?
- What is the impact of new players like Google, Microsoft, Facebook, Apple, etc. in this game, starting to design their own systems or processor SoCs?
Panelists
Jeffrey D. Brown
Distinguished Engineer, Emerging Product Development and Hardware Architect, SoC
IBM
Jeffrey D. Brown, IBM Server and Technology Group, is an IBM Distinguished Engineer and member of the IBM Academy of Technology. He received a B.Sc. in Electrical Engineering and a B.Sc. in Physics from Washington State University in 1981. He received his M.Sc. degree in Electrical Engineering from Washington State University in 1982. Mr. Brown has over 25 years of experience in VLSI development including processor, memory, and IO subsystem development projects for IBM multi-processor systems and servers. He is the coauthor of more than 40 patent filings. He has been the Chief Engineer on several processor and SOC chip development programs including Waternoose for the the Xbox 360® and IBM Power Edge of NetworkTM. Mr. Brown is presently the chair of the OpenPOWERTM Foundation Technical Steering Committee.
Norris Ip
Solutions Group Director
Cadence
Norris Ip is a Solutions Group Director of the Formal and Automated Verification business unit in the Systems & Verification Group at Cadence Design System. Norris joined Cadence in 2014 via the acquisition of Jasper, where he was a Fellow at Jasper Design Automation, focused on development of the formal verification platform for RTL development, architectural modeling, IP Register Verification, SoC Connectivity Verification, etc. Prior to joining Jasper, he was a Research Scientist at Cadence Berkeley Labs, developing formal and smart test bench techniques. He also served in the SystemC Verification Working Group.
He received a B.A (Honors) in Engineering and Computer Science from Oxford University in 1991, and a Ph.D. in Computer Science from Stanford University in 1997. Norris has over over 20 years of experience in advancing verification techniques for different application domains and is the coauthor of 19 US patents and patent filings.
Ram Krishnamurthy
Head of High Performance and Low Voltage Circuits Group
Intel Labs
Ram Krishnamurthy received the B.E. degree in electrical engineering from Regional Engineering College, Trichy, India, in 1993 and Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 1998. He has been with Intel Corporation since 1998, where he is Senior Principal Engineer and heads the high performance and low voltage circuits group at Circuits Research Labs, Intel Labs, Hillsboro, Oregon. He is responsible for research in high performance, energy efficient and low voltage circuits for microprocessors and SoCs, and has worked on circuits research for high performance and low power microprocessors on eight generations of Intel technologies.
He holds 95 issued patents with over 50 patents pending and has published 135 conference/journal papers and 3 book chapters on high-performance energy-efficient microprocessor design. He serves as Intel’s representative on the SRC Integrated Circuits and Systems Sciences Task Force, has been a guest editor of the IEEE Journal of Solid-State Circuits and on the technical program committees of the ISSCC, CICC, and SOCC conferences. He served as the Technical Program Chair/General Chair for the 2005/2006 IEEE International Systems-on-Chip Conference and presently serves on the conference’s steering committee. He serves as ECE department adjunct faculty at Oregon State University, where he taught advanced VLSI design. He also serves on industrial advisory board of Oregon State University and State University of New York at Buffalo ECE departments, and editorial boards of IEEE transactions on VLSI systems and IEEE journal of emerging circuits and systems.
Krishnamurthy has received the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award in 2012, IEEE European Solid State Circuits Conference Best Paper Award in 2012, Outstanding Industry Mentor Award from SRC in 2002 and 2011, Intel Awards for most patents filed in 2001 and most patents issued in 2003, Alumni recognition award from Carnegie Mellon University in 2009, and MIT Technology Review’s TR35 Innovator Award in 2006. He has received the Intel Achievement Award, Intel Corporation’s highest technical award, twice - in 2004 and 2008 for development and technology transfer of novel high-performance execution core arithmetic circuits and special-purpose hardware encryption accelerators. He is a Fellow of the IEEE.
Nigel Paver is an ARM Fellow with over 24 years of experience in and around the ARM architecture. He is the Director of Systems Research in the corporate R&D group leading a team investigating end-to-end systems power and performance across a range of emerging ARM market segments.
Nigel received his PhD in Computer Science from the University of Manchester in 1994 where we worked on the AMULET asynchronous implementations of the ARM architecture. He also holds an MS degree in Systems Design also from Manchester University and a BS degree in Electronics from UMIST. Nigel holds 31 US patents and has published in excess of 30 papers including best paper awards at; VLSI ’93, ASYNC ’97 & ASYNC ’98, ISPASS’14 and he received the British Computer Society (BCS) Award for his work on AMULET1.
Sakir Sezer
Director of Research, ECIT, Queen's University Belfast and CTO, titanic systems
