Here is a list of all papers that have been accepted for the conference.

Note that this list contains regular papers accepted for oral presentation, poster presentation, and Design Track papers.

We are working on a preliminary program schedule that will be available here soon.

A 10-BIT 250MS/S LOW-GLITCH BINARY-WEIGHTED DIGITAL-TO-ANALOG CONVERTER
Fang-Ting Chou and Chung-Chih Hung

A 40NM 256KB 6T SRAM WITH THRESHOLD POWER-GATING, LOW-SWING GLOBAL READ
BIT-LINE, AND CHARGE-SHARING WRITE WITH VTRIP-TRACKING AND NEGATIVE
SOURCE-LINE WRITE-ASSISTS
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te
Chuang, Ming-Hsien Tu, Yu-Hsuan Chen, Yong-Jyun Hu, Paul-Sen Kan,
Huan-Shun Huang, Kuen-Di Lee and Yung-Shin Kao

A BODY-BIAS BASED CURRENT SENSE AMPLIFIER FOR HIGH- SPEED LOW-POWER
EMBEDDED SRAMS
Tahseen Shakir and Manoj Sachdev

A BUFFERED FLOW CONTROL SCHEME WITH WEIGHTED BASED DROPPING FLIT
MECHANISM FOR EFFICIENT COMMUNICATION IN NOC
Ahmed Aldammas, Adel Soudani and Abdullah Al-Dhelaan

A CLOCK GENERATOR BASED ON MULTIPLYING DELAY-LOCKED LOOP
Chorng-Sii Hwang, Ting-Li Chu and Wen-Cheng Chen

A CMOS SELF-POWERED MONOLITHIC LIGHT DIRECTION SENSOR WITH SAR ADC
Hongjiang Song, Hongyi Wang, Zhijian Lu, Tao Luo and Jennifer Blain
Christen

A CONFIGURABLE PACKET CLASSIFICATION ARCHITECTURE FOR SOFTWARE-DEFINED
NETWORKING
Keissy Guerra Perez, Xin Yang, Sandra Scott-Hayward and Sakir Sezer

A FRAMEWORK FOR SPECIFYING, MODELING, IMPLEMENTATION AND VERIFICATION
OF SOC PROTOCOLS
Shahid Ikram, Isam Akkawi, Jack Perveiler, David Asher and Jim Ellis

A HARDWARE ACCELERATION SCHEME FOR MEMORY-EFFICIENT FLOW PROCESSING
Xin Yang, Sakir Sezer and Shane O'Neill

A HIGHLY SENSITIVE ISFET USING PH-TO-CURRENT CONVERSION FOR REAL-TIME
DNA SEQUENCING
Mohammad Uzzal, Payman Zarkesh-Ha, Jeremy Edwards, Ezequiel Coelho and
Priyanka Rawat

A LOW COMPLEXITY MULTI STANDARD DUAL BAND CMOS POLAR TRANSMITTER FOR
SMART UTILITY NETWORKS
Jan Henning Mueller, Ye Zhang, Lei Liao, Aytac Atac, Zhimiao Chen,
Bastian Mohr and Stefan Heinen

A LOW POWER CHARGE SHARING HIERARCHICAL BITLINE AND VOLTAGE-LATCHED
SENSE AMPLIFIER FOR SRAM MACRO IN 28 NM CMOS TECHNOLOGY
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang and
Reed Lee

A LOW SUPPLY VOLTAGE MIXED-SIGNAL MAXIMUM POWER POINT TRACKING
CONTROLLER FOR PHOTOVOLTAIC POWER SYSTEM
Jun-Hua Chiang, Bin-Da Liu, Shih-Ming Chen and Hong-Tzer Yang

A NEURAL REHABILITATION CHIP WITH NEURAL RECORDING, SPIKE DETECTION,
SPIKE RATE COUNTER, AND BIPHASIC NEURAL STIMULATOR
Hongjiang Song, Chen Chen, Meng-Wei Lin, Kaijun Li and Jennifer Blain
Christen

A NEW APPROACH USING SYMBOLIC ANALYSIS TO COMPUTE PATH-DEPENDENT
EFFECTIVE PROPERTIES PRESERVING HIERARCHY
Sridhar Srinivasan, Ellis Cohen and Mark Hofmann

A NEW DESIGN METHODOLOGY FOR VOLTAGE-TO-TIME CONVERTERS (VTCS)
CIRCUITS SUITABLE FOR TIME-BASED ANALOG-TO-DIGITAL CONVERTERS
(T-ADC)
M. Wagih Ismail and Hassan Mostafa

A NOVEL RATIOED LOGIC STYLE FOR FASTER SUBTHRESHOLD DIGITAL CIRCUITS
BASED ON 90 NM CMOS AND BELOW
Weiwei SHI and Chiu-sing CHOY

A POWER EFFICIENT RECONFIGURABLE SYSTEM-IN-STACK: 3D INTEGRATION OF
ACCELERATORS, FPGAS, AND DRAM
Peter Gadfort, Aravind Dasu, Ali Akoglu, Yoon Leow and Michael Fritze

A RECONFIGURABLE 0-L1-L2 S-MASH2 MODULATOR WITH HIGH-LEVEL SIZING AND
POWER ESTIMATION
Abhilash K N and Srinivas .M.B

A STOCHASTIC LEARNING ALGORITHM FOR NEUROMEMRISTIVE SYSTEMS
Cory Merkel and Dhireesha Kudithipudi

A SYSTEMATIC METHODOLOGY TO DESIGN HIGH POWER TERAHERTZ AND
MILLIMETER-WAVE AMPLIFIERS
Siavash Moghadami, Farzaneh JalaliBidgoli and Shahab Ardalan

A UNIQUE NON-INTRUSIVE APPROACH TO NON-ATE BASED CUL-DE-SAC SOC DEBUG
Vasant Easwaran, Virendra Bansal, Greg Shurtz, Rahul Gulati, Mihir
Mody, Prashant Karandikar and Prithvi Shankar Y.A.

ADAPTIVE MULTICAST ROUTING METHOD FOR 3D MESH-BASED NETWORKS-ON-CHIP
Poona Bahrebar, Azarakhsh Jalalvand and Dirk Stroobandt

AN 10GB/S INDUCTORLESS RECEIVER WITH ADAPTIVE EQUALIZATION AND CLOCK
ALIGNMENT IN 0.13~$\MU$M CMOS
Sushrant Monga and Shouri Chatterjee

AN ACCELERATED SUCCESSIVE APPROXIMATION TECHNIQUE FOR ANALOG TO DIGITAL
CONVERTER DESIGN
Haibo Wang and Ram Harshvardhan Radhakrishnan

AN ALL-DIGITAL ON-CHIP ABNORMAL TEMPERATURE WARNING SENSOR FOR DYNAMIC
THERMAL MANAGEMENT
Ching-Che Chung and Jhih-Wei Li

AN ENERGY EFFICIENT WIRELESS NETWORK-ON-CHIP USING POWER-GATED
TRANSCEIVERS
Hemanta Kumar Mondal and Sujay Deb

ANALYSIS OF THE CURRENT-VOLTAGE CHARACTERISTICS OF SILICON ON
FERROELECTRIC INSULATOR FIELD EFFECT TRANSISTOR (SOF-FET)
Azzedin Es-Sakhi and Masud Chowdhury

BENEFITS AND COSTS OF PREDICTION BASED DVFS FOR NOCS AT ROUTER LEVEL
Cristinel Ababei and Nicholas Mastronarde

BUS MODULATED THE REGULATOR
Zhang Lei, Mei Wangsheng and Meng Qing

CHANGING POWER OPTIMIZATION FOR FINFET TECHNOLOGY
Gerard M Blair and Bruce E Zahn

CM_ISA++: AN INSTRUCTION SET FOR DYNAMIC TASK SCHEDULING UNITS FOR MORE
THAN 1000 CORES
Oliver Arnold, Benedikt Noethen and Gerhard Fettweis

COLLISION ARRAY BASED WORKLOAD ASSIGNMENT FOR NETWORK-ON-CHIP
CONCURRENCY
He Zhou, Linda Powers and Janet Roveda

COMPARATIVE STUDY OF FINFETS VERSUS 22NM BULK CMOSS: SRAM DESIGN
PERSPECTIVE
Hooman Farkhani, Ali Peiravi and Farshad Moradi

COMPARISON BETWEEN OPTIMAL INTERCONNECTION NETWORK IN DIFFERENT 2D AND
3D NOC STRUCTURES
Farzad Radfar, Masoud Zabihi and Reza Sarvari

COMPENSATING IMPERFECTIONS IN RF-DAC BASED TRANSMITTERS USING LUT-BASED
PREDISTORTION
Bastian Mohr, Ye Zhang, Jan Henning Mueller and Stefan Heinen

COST-OPTIMAL DESIGN OF WIRELESS PRE-BONDING TEST FRAMEWORK
Unni Chandran, Danella Zhao and Rathish Jayabharathi

DESIGN AND IMPLEMENTATION OF NOVEL SOURCE SYNCHRONOUS INTERCONNECTION
IN MODERN GPU CHIPS
Tao Li and Greg Sadowski

DESIGN METHODOLOGY OF PROCESS VARIATION TOLERANT D-FLIP-FLOPS FOR LOW
VOLTAGE CIRCUIT OPERATION
Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera

DESIGN OF A 9-BIT 1GS/S CMOS FOLDING A/D CONVERTER WITH A BOUNDARY
ERROR REDUCTION TECHNIQUE.
Seongjoo Lee, Jongyoon Hwang, Munkyo Lee, Sunphil Nah and Minkyu Song

DESIGN OF A LOW POWER CMOS 10BIT FLASH-SAR ADC
Gi-Yoon Lee and Kwang-Sub Yoon

DESIGN OF A LOW POWER MULTISTANDARD TRANSCEIVER CHAIN BASED ON
CURRENT-REUSE VCO
Ye Zhang, Jan Henning Mueller, Muh-Dey Wei, Ralf Wunderlich and Stefan
Heinen

DESSERT: DESIGN SPACE EXPLORATION TOOL BASED ON POWER AND ENERGY AT
SYSTEM-LEVEL
Santhosh Kumar Rethinagiri, Oscar Palomar, Adrian Cristal, Osman Unsal
and Michael Swift

DEVELOPMENT OF A SYSTEM WITH DSP TECHNOLOGY FOR ENHANCING ELECTRONIC
NOSE PERFORMANCE
Cristhian Manuel Durán Acevedo and Isaac Torres López

ELECTROMYOGRAPH DATA ACQUISITION AND APPLICATION USING CYPRESS
PROGRAMMABLE SYSTEM ON CHIP
Shreeyash Salunke, Shreyas Darne, Keval Shah and Rishikesh Dhamapurkar

ENERGY AWARE APPROXIMATE DCT ARCHITECTURE TRADING QUALITY VIA BOUNDARY
ERROR-RESILIENCY
Bharat Garg, Nitesh K Bharadwaj and G K Sharma

ERRORS IN SOLVING INVERSE PROBLEM FOR REVERSING RTN EFFECTS ON VCCMIN
SHIFT IN SRAM RELIABLITY SCREENING TEST DESIGNS
Hiroyuki Yamauchi and Worawit Somha

EVALUATING MOBILE SOCS AS AN ENERGY EFFICIENT DSP PLATFORM
Matt Briggs and Payman Zarkesh-Ha

FLEXIBLE RECONFIGURABLE ARCHITECTURE FOR DSP APPLICATIONS
Abdulfattah Obeid, Zied Marrakchi, Hani Ghariani, Mohamed Abid,
Mohammed BenSaleh and Habib Mehrez

HARDWARE ARCHITECTURE OF AN INTERNET PROTOCOL VERSION 6 PROCESSOR
Boris Traskov, Ulrich Langenbach, Klaus Hofmann and Peter Gregorius

HETEROGENEOUS PHOTONIC NETWORK-ON-CHIP WITH DYNAMIC BANDWIDTH
ALLOCATION
Ankit Shah, Naseef Mansoor, Ben Johnstone, Amlan Ganguly and Sonia
Lopez-Alarcon

HIGH PERFORMANCE FAULT TOLERANT MEMORY MANAGEMENT UNIT FOR SPACE
APPLICATIONS
xiaofang chen, tianfang niu and sharon lim

HIGH-FREQUENCY AND POWER-EFFICIENCY ULTRASOUND BEAM-FORMING PROCESSOR
FOR HANDHELD APPLICATIONS
Guo-Zua Wu, Song-Nien Tang, Chih-Chi Chang, Chien-Ju Lee, Kuan-Hsien
Lin and Oscal T.-C. Chen

IP WATERMARK VERIFICATION BASED ON POWER CONSUMPTION ANALYSIS
Cédric Marchand, Lilian Bossuet and Edward Jung

LOW-POWER HIGH-SPEED ON-CHIP ASYNCHRONOUS WAVE-PIPELINED CML SERDES
Ashok Jaiswal, Dominik Walk, Yuan Fang and Klaus Hofmann

METHODOLOGY OF EXPLORING ESL/RTL MANY-CORE PLATFORMS FOR DEVELOPING
EMBEDDED PARALLEL APPLICATIONS
Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua
Yeh, Liang-Chia Cheng and Juin-Ming Lu

MICROCELLS FOR ICA-SOC FOR REMOTE SENSING OF HIGH ENERGY RADIATION
Vijay Jain

MITH-DYN : A MULTI VTH DYNAMIC LOGIC DESIGN STYLE USING MIXED MODE
FINFETS
Ramesh Nair and Ranga Vemuri

MODULE-BASED BUS GATING METHODOLOGY IN LOW POWER SOC DESIGN
Zhe Ge, Jinglin Zhang and Miaolin Tan

MULTICHANNEL TUNNELING CARBON NANOTUBE FIELD EFFECT TRANSISTOR
(MT-CNTFET)
Azzedin Es-Sakhi and Masud Chowdhury

MULTILAYER LAYER GRAPHENE NANORIBBON FLASH MEMORY:ANALYSIS OF
PROGRAMMING AND ERASING OPERATION
Nahid Hossain, Masud Chowdhury and Md Belayat Hossain

NETWORKS ON CHIP DESIGN FOR REAL-TIME SYSTEMS
Ali Mahdoum

NEW QUANTIZATION ERROR ASSESSMENT METHODOLOGY FOR FIXED-POINT PIPELINE
FFT PROCESSOR DESIGN
Chen Yang, Yizhuang Xie and Yi Deng

NEW TRENDS IN TSV: SWCNT-BASED TSV, AIR-GAP BASED COAXIAL TSV, AND
ADIABATIC TSV
khaled salah

ON CIRCUIT DESIGN OF ON-CHIP NON-BLOCKING INTERCONNECTION NETWORKS
Yikun Jiang and Mei Yang

ON WIRING DELAYS REDUCTION OF TREE-BASED FPGA USING 3-D FABRIC
zied marrakchi, vinod pangracious and habib mehrez

POWER AWARE PARALLEL COMPUTING ON ASYMMETRIC MULTIPROCESSOR
Sheheeda Manakkadu and Nazeih Botros

PVT-AWARE DIGITAL CONTROLLED VOLTAGE REGULATOR DESIGN FOR
ULTRA-LOW-POWER (ULP) DVFS SYSTEMS
Pei-Chen Wu, Yi-Ping Kuo and Wei Hwang

REDUCING THE TURN-ON TIME AND OVERSHOOT VOLTAGE FOR A DIODE-TRIGGERED
SILICON-CONTROLLED RECTIFIER DURING AN ELECTROSTATIC DISCHARGE EVENT
Ahmed Ginawi

REFLEX: RECONFIGURABLE LOGIC FOR ENTROPY EXTRACTION
Vikram Suresh and Wayne Burleson

RELIABILITY AWARE LOGIC SYNTHESIS THROUGH REWRITING
Satish Grandhi, Christian Spagnol, Jiaoyan Chen, Emanuel Popovici and
Sorin Cotafona

RESISTORLESS ON-DIE HIGH VOLTAGE POWER SUPPLY NOISE MEASUREMENT
Siddharth Katare, Raj Dua and Narayanan Natarajan

ROBUST LOW-VOLTAGE 7T-SRAM CELL FOR LOW-POWER APPLICATIONS
Farshad Moradi and Jens Madsen

RUN-TIME VOLTAGE DETECTION CIRCUIT FOR 3-D IC POWER DELIVERY
Divya Pathak and Ioannis Savidis

SOC SCAN-CHAIN VERIFICATION UTILIZING FPGA-BASED EMULATION PLATFORM AND
SCE-MI INTERFACE
Bill Jason Pidlaoan Tomas, Yingtao Jiang and Mei Yang

SUPERCAPACITOR-BASED ENERGY HARVESTER SYSTEM DESIGN
Moeen Hassanalieragh, Tolga Soyata, Andrew Nadeau and Gaurav Sharma

THERMAL-AWARE MEMORY MANAGEMENT UNIT OF 3D-STACKED DRAM FOR 3D HIGH
DEFINITION (HD) VIDEO
Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang and
Wei Hwang

TIME STRETCHER FOR A TIME-TO-DIGITAL CONVERTER WITH A PRECISELY MATCHED
CURRENT MIRROR
Muhammad Tanveer, Johan Borg and Jonny Johansson

TOWARDS PLATFORM LEVEL POWER MANAGEMENT IN MOBILE SYSTEMS
David Kadjo, Umit Ogras, Raid Ayoub, Micheal Kishinevsky and Paul Gratz

VARIATION-AWARE FLIP-FLOP ENERGY OPTIMIZATION FOR ULTRA LOW VOLTAGE
OPERATION
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara and Hidetoshi
Onodera

VERY FAST CO-SIMULATION MODEL AND ACCURATE ON-THE-FLY PERFORMANCE
ESTIMATION METHODOLOGY FOR HETEROGENEOUS MPSOC
Nicolas Serna and Francois Verdier

WIRING RESOURCE MINIMIZATION FOR PHYSICALLY-COMPLEX NETWORK-ON-CHIP
ARCHITECTURES
Nickvash Kani and Azad Naeemi