7:30AM – 10:00AM

Registration

8:30AM – 10:00AM

T1A (Rm TBD)
M. Tehranipoor
Univ. of Connecticut

Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits

T1B (Rm TBD)
P. Pande², A. Nojeh¹, A. Ivanov^1
1Univ. of British Columbia, Canada
²Washington State Univ

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

10:00AM – 10:30AM

Coffee break

10:30AM – 12:00PM

T2A (Rm TBD)
G.M. Blair
Avago

Clock Implementation: A Question of Timing

T2B (Rm TBD)
A. Nojeh¹, P. Pande², A. Ivanov^1
1Univ. of British Columbia, Canada
²Washington State Univ

Carbon Nanotubes and Opportunities for Wireless On-Chip Interconnect

12:00PM – 1:30PM

Lunch break

1:30PM – 3:00PM

T3A (Rm TBD)
U.Y. Ogras
Arizona State Univ.

Design and Management of Multiprocessor System-on-Chips

T3B (Rm TBD)
H. Sun
Infinera

Recent Advancements in Fiber Optic Transmission Enabled by Highly Integrated Mixed Signal SoC and Advanced Digital Signal Processing

3:00PM – 3:30PM

Coffee break

3:30PM – 5:00PM

T4A (Rm TBD)
A. Marshall
Univ. of Texas in Dallas

System-on-Chip Design Using Tri-Gate Technology

T4B (Rm TBD)
W. Kunz, D. Stoffel, J. Urdahl
Univ. of Kaiserslautem, Germany

Formal Verification in System-on-Chip Design: Scientific Foundations and Practical Methodology