Here is a list of all papers that have been accepted for the conference.

Note that this list contains regular papers accepted for oral presentation, poster presentation, and Design Track papers.

We are working on a preliminary program schedule that will be available here soon.

A 10-BIT 250MS/S LOW-GLITCH BINARY-WEIGHTED DIGITAL-TO-ANALOG CONVERTER
Fang-Ting Chou and Chung-Chih Hung

A 40NM 256KB 6T SRAM WITH THRESHOLD POWER-GATING, LOW-SWING GLOBAL READ
BIT-LINE, AND CHARGE-SHARING WRITE WITH VTRIP-TRACKING AND NEGATIVE
SOURCE-LINE WRITE-ASSISTS
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te
Chuang, Ming-Hsien Tu, Yu-Hsuan Chen, Yong-Jyun Hu, Paul-Sen Kan,
Huan-Shun Huang, Kuen-Di Lee and Yung-Shin Kao

A BODY-BIAS BASED CURRENT SENSE AMPLIFIER FOR HIGH- SPEED LOW-POWER
EMBEDDED SRAMS
Tahseen Shakir and Manoj Sachdev

A BUFFERED FLOW CONTROL SCHEME WITH WEIGHTED BASED DROPPING FLIT
MECHANISM FOR EFFICIENT COMMUNICATION IN NOC
Ahmed Aldammas, Adel Soudani and Abdullah Al-Dhelaan

A CLOCK GENERATOR BASED ON MULTIPLYING DELAY-LOCKED LOOP
Chorng-Sii Hwang, Ting-Li Chu and Wen-Cheng Chen

A CMOS SELF-POWERED MONOLITHIC LIGHT DIRECTION SENSOR WITH SAR ADC
Hongjiang Song, Hongyi Wang, Zhijian Lu, Tao Luo and Jennifer Blain
Christen

A CONFIGURABLE PACKET CLASSIFICATION ARCHITECTURE FOR SOFTWARE-DEFINED
NETWORKING
Keissy Guerra Perez, Xin Yang, Sandra Scott-Hayward and Sakir Sezer

A FRAMEWORK FOR SPECIFYING, MODELING, IMPLEMENTATION AND VERIFICATION
OF SOC PROTOCOLS
Shahid Ikram, Isam Akkawi, Jack Perveiler, David Asher and Jim Ellis

A HARDWARE ACCELERATION SCHEME FOR MEMORY-EFFICIENT FLOW PROCESSING
Xin Yang, Sakir Sezer and Shane O'Neill

A HIGHLY SENSITIVE ISFET USING PH-TO-CURRENT CONVERSION FOR REAL-TIME
DNA SEQUENCING
Mohammad Uzzal, Payman Zarkesh-Ha, Jeremy Edwards, Ezequiel Coelho and
Priyanka Rawat

A LOW COMPLEXITY MULTI STANDARD DUAL BAND CMOS POLAR TRANSMITTER FOR
SMART UTILITY NETWORKS
Jan Henning Mueller, Ye Zhang, Lei Liao, Aytac Atac, Zhimiao Chen,
Bastian Mohr and Stefan Heinen

A LOW POWER CHARGE SHARING HIERARCHICAL BITLINE AND VOLTAGE-LATCHED
SENSE AMPLIFIER FOR SRAM MACRO IN 28 NM CMOS TECHNOLOGY
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang and
Reed Lee

A LOW SUPPLY VOLTAGE MIXED-SIGNAL MAXIMUM POWER POINT TRACKING
CONTROLLER FOR PHOTOVOLTAIC POWER SYSTEM
Jun-Hua Chiang, Bin-Da Liu, Shih-Ming Chen and Hong-Tzer Yang

A NEURAL REHABILITATION CHIP WITH NEURAL RECORDING, SPIKE DETECTION,
SPIKE RATE COUNTER, AND BIPHASIC NEURAL STIMULATOR
Hongjiang Song, Chen Chen, Meng-Wei Lin, Kaijun Li and Jennifer Blain
Christen

A NEW APPROACH USING SYMBOLIC ANALYSIS TO COMPUTE PATH-DEPENDENT
EFFECTIVE PROPERTIES PRESERVING HIERARCHY
Sridhar Srinivasan, Ellis Cohen and Mark Hofmann

A NEW DESIGN METHODOLOGY FOR VOLTAGE-TO-TIME CONVERTERS (VTCS)
CIRCUITS SUITABLE FOR TIME-BASED ANALOG-TO-DIGITAL CONVERTERS
(T-ADC)
M. Wagih Ismail and Hassan Mostafa

A NOVEL RATIOED LOGIC STYLE FOR FASTER SUBTHRESHOLD DIGITAL CIRCUITS
BASED ON 90 NM CMOS AND BELOW
Weiwei SHI and Chiu-sing CHOY

A POWER EFFICIENT RECONFIGURABLE SYSTEM-IN-STACK: 3D INTEGRATION OF
ACCELERATORS, FPGAS, AND DRAM
Peter Gadfort, Aravind Dasu, Ali Akoglu, Yoon Leow and Michael Fritze

A RECONFIGURABLE 0-L1-L2 S-MASH2 MODULATOR WITH HIGH-LEVEL SIZING AND
POWER ESTIMATION
Abhilash K N and Srinivas .M.B

A STOCHASTIC LEARNING ALGORITHM FOR NEUROMEMRISTIVE SYSTEMS
Cory Merkel and Dhireesha Kudithipudi

A SYSTEMATIC METHODOLOGY TO DESIGN HIGH POWER TERAHERTZ AND
MILLIMETER-WAVE AMPLIFIERS
Siavash Moghadami, Farzaneh JalaliBidgoli and Shahab Ardalan

A UNIQUE NON-INTRUSIVE APPROACH TO NON-ATE BASED CUL-DE-SAC SOC DEBUG
Vasant Easwaran, Virendra Bansal, Greg Shurtz, Rahul Gulati, Mihir
Mody, Prashant Karandikar and Prithvi Shankar Y.A.

ADAPTIVE MULTICAST ROUTING METHOD FOR 3D MESH-BASED NETWORKS-ON-CHIP
Poona Bahrebar, Azarakhsh Jalalvand and Dirk Stroobandt

AN 10GB/S INDUCTORLESS RECEIVER WITH ADAPTIVE EQUALIZATION AND CLOCK
ALIGNMENT IN 0.13~$\MU$M CMOS
Sushrant Monga and Shouri Chatterjee

AN ACCELERATED SUCCESSIVE APPROXIMATION TECHNIQUE FOR ANALOG TO DIGITAL
CONVERTER DESIGN
Haibo Wang and Ram Harshvardhan Radhakrishnan

AN ALL-DIGITAL ON-CHIP ABNORMAL TEMPERATURE WARNING SENSOR FOR DYNAMIC
THERMAL MANAGEMENT
Ching-Che Chung and Jhih-Wei Li

AN ENERGY EFFICIENT WIRELESS NETWORK-ON-CHIP USING POWER-GATED
TRANSCEIVERS
Hemanta Kumar Mondal and Sujay Deb

ANALYSIS OF THE CURRENT-VOLTAGE CHARACTERISTICS OF SILICON ON
FERROELECTRIC INSULATOR FIELD EFFECT TRANSISTOR (SOF-FET)
Azzedin Es-Sakhi and Masud Chowdhury

BENEFITS AND COSTS OF PREDICTION BASED DVFS FOR NOCS AT ROUTER LEVEL
Cristinel Ababei and Nicholas Mastronarde

BUS MODULATED THE REGULATOR
Zhang Lei, Mei Wangsheng and Meng Qing

CHANGING POWER OPTIMIZATION FOR FINFET TECHNOLOGY
Gerard M Blair and Bruce E Zahn

CM_ISA++: AN INSTRUCTION SET FOR DYNAMIC TASK SCHEDULING UNITS FOR MORE
THAN 1000 CORES
Oliver Arnold, Benedikt Noethen and Gerhard Fettweis

COLLISION ARRAY BASED WORKLOAD ASSIGNMENT FOR NETWORK-ON-CHIP
CONCURRENCY
He Zhou, Linda Powers and Janet Roveda

COMPARATIVE STUDY OF FINFETS VERSUS 22NM BULK CMOSS: SRAM DESIGN
PERSPECTIVE
Hooman Farkhani, Ali Peiravi and Farshad Moradi

COMPARISON BETWEEN OPTIMAL INTERCONNECTION NETWORK IN DIFFERENT 2D AND
3D NOC STRUCTURES
Farzad Radfar, Masoud Zabihi and Reza Sarvari

COMPENSATING IMPERFECTIONS IN RF-DAC BASED TRANSMITTERS USING LUT-BASED
PREDISTORTION
Bastian Mohr, Ye Zhang, Jan Henning Mueller and Stefan Heinen

COST-OPTIMAL DESIGN OF WIRELESS PRE-BONDING TEST FRAMEWORK
Unni Chandran, Danella Zhao and Rathish Jayabharathi

DESIGN AND IMPLEMENTATION OF NOVEL SOURCE SYNCHRONOUS INTERCONNECTION
IN MODERN GPU CHIPS
Tao Li and Greg Sadowski

DESIGN METHODOLOGY OF PROCESS VARIATION TOLERANT D-FLIP-FLOPS FOR LOW
VOLTAGE CIRCUIT OPERATION
Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera

DESIGN OF A 9-BIT 1GS/S CMOS FOLDING A/D CONVERTER WITH A BOUNDARY
ERROR REDUCTION TECHNIQUE.
Seongjoo Lee, Jongyoon Hwang, Munkyo Lee, Sunphil Nah and Minkyu Song

DESIGN OF A LOW POWER CMOS 10BIT FLASH-SAR ADC
Gi-Yoon Lee and Kwang-Sub Yoon

DESIGN OF A LOW POWER MULTISTANDARD TRANSCEIVER CHAIN BASED ON
CURRENT-REUSE VCO
Ye Zhang, Jan Henning Mueller, Muh-Dey Wei, Ralf Wunderlich and Stefan
Heinen

DESSERT: DESIGN SPACE EXPLORATION TOOL BASED ON POWER AND ENERGY AT
SYSTEM-LEVEL
Santhosh Kumar Rethinagiri, Oscar Palomar, Adrian Cristal, Osman Unsal
and Michael Swift

DEVELOPMENT OF A SYSTEM WITH DSP TECHNOLOGY FOR ENHANCING ELECTRONIC
NOSE PERFORMANCE
Cristhian Manuel Durán Acevedo and Isaac Torres López

ELECTROMYOGRAPH DATA ACQUISITION AND APPLICATION USING CYPRESS
PROGRAMMABLE SYSTEM ON CHIP
Shreeyash Salunke, Shreyas Darne, Keval Shah and Rishikesh Dhamapurkar

ENERGY AWARE APPROXIMATE DCT ARCHITECTURE TRADING QUALITY VIA BOUNDARY
ERROR-RESILIENCY
Bharat Garg, Nitesh K Bharadwaj and G K Sharma

ERRORS IN SOLVING INVERSE PROBLEM FOR REVERSING RTN EFFECTS ON VCCMIN
SHIFT IN SRAM RELIABLITY SCREENING TEST DESIGNS
Hiroyuki Yamauchi and Worawit Somha

EVALUATING MOBILE SOCS AS AN ENERGY EFFICIENT DSP PLATFORM
Matt Briggs and Payman Zarkesh-Ha

FLEXIBLE RECONFIGURABLE ARCHITECTURE FOR DSP APPLICATIONS
Abdulfattah Obeid, Zied Marrakchi, Hani Ghariani, Mohamed Abid,
Mohammed BenSaleh and Habib Mehrez

HARDWARE ARCHITECTURE OF AN INTERNET PROTOCOL VERSION 6 PROCESSOR
Boris Traskov, Ulrich Langenbach, Klaus Hofmann and Peter Gregorius

HETEROGENEOUS PHOTONIC NETWORK-ON-CHIP WITH DYNAMIC BANDWIDTH
ALLOCATION
Ankit Shah, Naseef Mansoor, Ben Johnstone, Amlan Ganguly and Sonia
Lopez-Alarcon

HIGH PERFORMANCE FAULT TOLERANT MEMORY MANAGEMENT UNIT FOR SPACE
APPLICATIONS
xiaofang chen, tianfang niu and sharon lim

HIGH-FREQUENCY AND POWER-EFFICIENCY ULTRASOUND BEAM-FORMING PROCESSOR
FOR HANDHELD APPLICATIONS
Guo-Zua Wu, Song-Nien Tang, Chih-Chi Chang, Chien-Ju Lee, Kuan-Hsien
Lin and Oscal T.-C. Chen

IP WATERMARK VERIFICATION BASED ON POWER CONSUMPTION ANALYSIS
Cédric Marchand, Lilian Bossuet and Edward Jung

LOW-POWER HIGH-SPEED ON-CHIP ASYNCHRONOUS WAVE-PIPELINED CML SERDES
Ashok Jaiswal, Dominik Walk, Yuan Fang and Klaus Hofmann

METHODOLOGY OF EXPLORING ESL/RTL MANY-CORE PLATFORMS FOR DEVELOPING
EMBEDDED PARALLEL APPLICATIONS
Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua
Yeh, Liang-Chia Cheng and Juin-Ming Lu

MICROCELLS FOR ICA-SOC FOR REMOTE SENSING OF HIGH ENERGY RADIATION
Vijay Jain

MITH-DYN : A MULTI VTH DYNAMIC LOGIC DESIGN STYLE USING MIXED MODE
FINFETS
Ramesh Nair and Ranga Vemuri

MODULE-BASED BUS GATING METHODOLOGY IN LOW POWER SOC DESIGN
Zhe Ge, Jinglin Zhang and Miaolin Tan

MULTICHANNEL TUNNELING CARBON NANOTUBE FIELD EFFECT TRANSISTOR
(MT-CNTFET)
Azzedin Es-Sakhi and Masud Chowdhury

MULTILAYER LAYER GRAPHENE NANORIBBON FLASH MEMORY:ANALYSIS OF
PROGRAMMING AND ERASING OPERATION
Nahid Hossain, Masud Chowdhury and Md Belayat Hossain

NETWORKS ON CHIP DESIGN FOR REAL-TIME SYSTEMS
Ali Mahdoum

NEW QUANTIZATION ERROR ASSESSMENT METHODOLOGY FOR FIXED-POINT PIPELINE
FFT PROCESSOR DESIGN
Chen Yang, Yizhuang Xie and Yi Deng

NEW TRENDS IN TSV: SWCNT-BASED TSV, AIR-GAP BASED COAXIAL TSV, AND
ADIABATIC TSV
khaled salah

ON CIRCUIT DESIGN OF ON-CHIP NON-BLOCKING INTERCONNECTION NETWORKS
Yikun Jiang and Mei Yang

ON WIRING DELAYS REDUCTION OF TREE-BASED FPGA USING 3-D FABRIC
zied marrakchi, vinod pangracious and habib mehrez

POWER AWARE PARALLEL COMPUTING ON ASYMMETRIC MULTIPROCESSOR
Sheheeda Manakkadu and Nazeih Botros

PVT-AWARE DIGITAL CONTROLLED VOLTAGE REGULATOR DESIGN FOR
ULTRA-LOW-POWER (ULP) DVFS SYSTEMS
Pei-Chen Wu, Yi-Ping Kuo and Wei Hwang

REDUCING THE TURN-ON TIME AND OVERSHOOT VOLTAGE FOR A DIODE-TRIGGERED
SILICON-CONTROLLED RECTIFIER DURING AN ELECTROSTATIC DISCHARGE EVENT
Ahmed Ginawi

REFLEX: RECONFIGURABLE LOGIC FOR ENTROPY EXTRACTION
Vikram Suresh and Wayne Burleson

RELIABILITY AWARE LOGIC SYNTHESIS THROUGH REWRITING
Satish Grandhi, Christian Spagnol, Jiaoyan Chen, Emanuel Popovici and
Sorin Cotafona

RESISTORLESS ON-DIE HIGH VOLTAGE POWER SUPPLY NOISE MEASUREMENT
Siddharth Katare, Raj Dua and Narayanan Natarajan

ROBUST LOW-VOLTAGE 7T-SRAM CELL FOR LOW-POWER APPLICATIONS
Farshad Moradi and Jens Madsen

RUN-TIME VOLTAGE DETECTION CIRCUIT FOR 3-D IC POWER DELIVERY
Divya Pathak and Ioannis Savidis

SOC SCAN-CHAIN VERIFICATION UTILIZING FPGA-BASED EMULATION PLATFORM AND
SCE-MI INTERFACE
Bill Jason Pidlaoan Tomas, Yingtao Jiang and Mei Yang

SUPERCAPACITOR-BASED ENERGY HARVESTER SYSTEM DESIGN
Moeen Hassanalieragh, Tolga Soyata, Andrew Nadeau and Gaurav Sharma

THERMAL-AWARE MEMORY MANAGEMENT UNIT OF 3D-STACKED DRAM FOR 3D HIGH
DEFINITION (HD) VIDEO
Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang and
Wei Hwang

TIME STRETCHER FOR A TIME-TO-DIGITAL CONVERTER WITH A PRECISELY MATCHED
CURRENT MIRROR
Muhammad Tanveer, Johan Borg and Jonny Johansson

TOWARDS PLATFORM LEVEL POWER MANAGEMENT IN MOBILE SYSTEMS
David Kadjo, Umit Ogras, Raid Ayoub, Micheal Kishinevsky and Paul Gratz

VARIATION-AWARE FLIP-FLOP ENERGY OPTIMIZATION FOR ULTRA LOW VOLTAGE
OPERATION
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara and Hidetoshi
Onodera

VERY FAST CO-SIMULATION MODEL AND ACCURATE ON-THE-FLY PERFORMANCE
ESTIMATION METHODOLOGY FOR HETEROGENEOUS MPSOC
Nicolas Serna and Francois Verdier

WIRING RESOURCE MINIMIZATION FOR PHYSICALLY-COMPLEX NETWORK-ON-CHIP
ARCHITECTURES
Nickvash Kani and Azad Naeemi

Wednesday Keynote Speaker

Tom Beckley
Senior Vice President of R&D
Cadence Design Systems, Inc.
“The Internet of Every-Thing: EDA Perspectives”

Tom Beckley is senior vice president of the Custom IC & PCB Group. His product responsibilities include the Virtuoso ® design environment, physical design and routing, and simulation product lines for full-custom digital and analog design, infrastructure such as the Open Access database and the process design kits (PDKs) that are essential for physical IC design, and for the Allegro® and OrCAD® design and routing, and Sigrity™ high-speed analysis solutions for printed circuit boards and IC packaging. In addition, Beckley is executive sponsor of the Cadence Quality Initiative, a sustained corporate focus on developing and deploying processes enabling design, implementation and delivery of high-quality, full-featured products.

Beckley joined Cadence in 2004 via the acquisition of Neolinear, where he served as President and CEO. Neolinear developed innovative auto-interactive and automated analog/RF tools and solutions for mixed-signal design. Prior to Neolinear, Beckley was head of the Systems Division at Avant! Corporation. He came to Avant! through the acquisition of Xynetix Design Systems, the market leader in advanced IC packaging and systems-level virtual prototyping, where he was President and CEO. Prior to Xynetix, Beckley held engineering and management positions at Harris Corporation and General Motors.

Beckley received his BS in mathematics and physics from Kalamazoo College and an MBA from Vanderbilt University.

Abstract:

A decade ago it was easy to tell who the semiconductor industry players were, and where they fit relative to customer requirements and the electronics ecosystem. Integrated Circuits, system and software each had their own distinct suppliers and there was a built-in assumption that customers would be able to “make it work”. Today, innovative connected products increasingly require a different paradigm where traditional industry definitions are blurred by the realization that the “Internet of Every-thing” requires a more unified knowledge of products and design solutions   in areas from devices to servers, software and infrastructure. This talk will address the challenges and provide visions from EDA perspectives as a key enabler of tomorrow’s technology on these changing industry dynamics - one in which is the need of integrated EDA solutions to meet requirements for increased miniaturization, mixed-signal design, sensors, software and electro-mechanical designs, to enable emerging vertical integrated systems companies and others to prosper.

Wednesday Plenary Speaker

Scott Runner
VP of advanced methodologies and low-power design
Qualcomm
“SoCs for Mobile Applications:  Systems from 0 MPH to over 100 MPH”

Scott Runner is currently the Vice President of Advanced Methodologies and Low Power Design at Qualcomm Technologies, Inc. He has worked in engineering in the semiconductor and EDA industries for 30 years, holding positions as Director of processors and IP, Design Automation and design manager at Conexant Systems Inc., a "founding" member of the DesignWare team at Synopsys Inc., and DSP and ASIC design engineer and Design Center manager at Fujitsu Microelectronics. He has taped out over 48 devices and has authored over 22 papers & articles. He holds a B.S. in Physics with emphasis in Computer Science and EE from Georgia Tech.

Abstract:

Mobile Applications are not only becoming more complex, but they are facing stiff constraints in power and quality & reliability. In the next decade, consumers are going to be treated to an array of new use case experiences in mobility that one can only dream of today. And new areas are emerging with exciting new user experiences in the car, with features known to many smartphone users making their way into the automobile, along with a myriad of other functions that drivers today cannot imagine. The HW and SW IP and systems integration that will enable these experiences are prodigious.   Design and verification challenges which must be surmounted to enable such high levels of integration and functionality are daunting.  And doing so in the timeframes required to satisfy the appetites of smartphone, tablet and automotive customers, while delivering to cost, power, performance and quality targets demands novel approaches.  We will explore these challenges in the design of the most popular devices in the wireless world.

Thursday Keynote Speaker

J. Thomas Pawlowski
Fellow and Chief Technologist
Micron Technology, Inc.
“The Future of Memory/Logic Technologies and Computing System Architectures”

J. Thomas Pawlowski is a Fellow and Chief Technologist with Micron’s Architecture Development Group. His responsibilities include evaluating new technologies and investments, exploring new memory and system architectures, and providing guidance to many technical teams, both internally and external to Micron.

Mr. Pawlowski’s experience includes the creation or co-creation of numerous groundbreaking memory architectures and concepts including: synchronous burst pipelined SRAM; hierarchical cache systems; Zero Bus Turnaround SRAM; the first double data rate memory (starting with SRAM and extending to DRAM and NAND technologies); PSRAM; high-speed NAND; the first double address rate memory; the first quad data rate memory; the first multi-channel memory; memories on SERDES buses; RLDRAM (the first DRAM to exceed SRAM performance); refresh and error correction schemes for memory subsystems; the architectural roots of Micron’s HMC device; the first dedicated hardware architecture of Micron’s newly announced nondeterministic Automata Processor; and other projects still in development.

Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada. He also holds approximately 150 U.S. and international patents and serves on several advisory boards, including the Exascale Grand Challenge EAB.

In his spare time, Mr. Pawlowski designs and builds loudspeakers and custom tools, and he has completed 60% of the design of a revolutionary electric car concept.

Abstract:

There is no shortage of scaling challenges facing the computing world: logic and memory scaling, dark silicon, thermal issues, bandwidth, throughput, energy proportionality, and many others. This talk will address these challenges, showing from whence we came and whither we are going. It will paint a picture of the increasing importance and influence of memory technologies and architectures on system performance metrics, discuss the underlying causes, and show the inevitable progression of the relationship between logic and memory.  The talk will then turn to Micron’s Automata Processing technology.

The Automata Processor is a fundamentally new computing architecture that leverages the intrinsic parallelism of DRAM. This innovative, nondeterministic, finite Automata Processor tackles NP-hard problems that, until now, have been considered unsolvable—opening up new frontiers of computing. The revelation of the Automata Processor portends a future rich in devices that have memory technology at their core.

Thursday Plenary Speaker

Jeffrey D. Brown
Distinguished Engineer, Emerging Product Development and Hardware Architect, SoC
IBM
"The Next Generation of Scale-Out Server Architecture : Building the OpenPOWER^TM Eco-System"

Jeffrey D. Brown, IBM Server and Technology Group, is an IBM Distinguished Engineer and member of the IBM Academy of Technology.  He received a B.Sc. in Electrical Engineering and a B.Sc. in Physics from Washington State University in 1981.  He received his M.Sc. degree in Electrical Engineering from Washington State University in 1982.  Mr. Brown has over 25 years of experience in VLSI development including processor, memory, and IO subsystem development projects for IBM multi-processor systems and servers.  He is the coauthor of more than 40 patent filings.  He has been the Chief Engineer on several processor and SOC chip development programs including Waternoose for the the Xbox 360^® and IBM Power Edge of Network^TM.  Mr. Brown is presently the chair of the OpenPOWER^TM Foundation Technical Steering Committee.

Abstract:

The elephant in the data center is that the price/performance improvement driven by CMOS technology scaling has slowed.  Manufacturing costs, power density, and thermal considerations are limiting the ability of developers to exploit the density and performance value of the next technology generation. IBM has partnered with more than 45 companies in the OpenPOWERTM Foundation to open up IBM POWER® systems and processors as a platform for innovation to overcome this problem. The OpenPOWERTM Foundation members are using the POWER8TM design, accelerators, and heterogenous computing to bring forth the next wave of performance scaling. This presentation will explore the motivation, strategy, and key technologies that are being brought to market by foundation members to meet this challenge.

Banquet Speaker

Paul Eremenko
Director, Project Ara
Google
“Democratizing the mobile hardware ecosystem: Google's Project Ara”

Paul Eremenko is currently director of Project Ara at Google, in the Advanced Technology & Projects (ATAP) organization. Previously he was an associate vice president at Motorola, where he led the development of Ara, a project to create a modular hardware ecosystem ­- rivaling the mobile app ecosystem in pace and level of innovation - around smartphones in an effort to deliver the mobile internet to the next 5 billion people. Paul is also a research affiliate at MIT in the Engineering Systems Division.

Prior to joining Motorola and then Google, Paul directed the Tactical Technology Office (TTO) at the Defense Advanced Research Projects Agency (DARPA), the Pentagon’s principal engine for disruptive innovation. TTO is DARPA’s systems office responsible for all X--‐plane, spacecraft, ground vehicle, and robotics programs, totalling approximately $500 million annually. Previously, Paul developed and led DARPA's advanced design and manufacturing program portfolio, and also served as program manager for several space efforts, including the 100 Year Starship.

Earlier in his career, Paul was an aerospace design engineer, the chief engineer for an unmanned aircraft program, and a management consultant focusing on technology, innovation, and M&A strategies. He has undergraduate and Master's degrees in aeronautics from MIT and Caltech, respectively, and a law degree from Georgetown University. Paul is also a licensed pilot.

Abstract:

Project Ara is an effort in Google’s Advanced Technology & Projects (ATAP) organization to create a modular smartphone platform, with the twin aims of delivering a deep customization experience to users and enabling significantly lowered barrier to entry into the mobile hardware ecosystem. The talk will describe the philosophical underpinnings of Project Ara, its status and timeline, and the opportunities it creates in the mobile processor space as an example. We will also talk about the origins of ATAP and its unique innovation model, inspired by that of the Defense Advanced Research Projects Agency (DARPA).Project Ara is an effort in Google's Advanced Technology & Projects (ATAP) organization to create a modular smartphone platform, with the twin aims of delivering a deep customization experience to users and enabling significantly lowered barrier to entry into the mobile hardware ecosystem. The talk will describe the philosophical underpinnings of Project Ara, its status and timeline, and the opportunities it creates in the mobile processor space as an example. We will also talk about the origins of ATAP and its unique innovation model, inspired by that of the Defense Advanced Research Projects Agency (DARPA).

SOCC 2014 Tutorial Day Program

September 2, 2014